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Winch: implement rmw and, xor and or for x64 (#10023)
* implement atomic rmw and, or, xor implement rmw or implement atomic rmw xor fix operand sizes implement and, or, xor update rmw or tests update rmw xor tests fmt use ad-hoc conversion for AtomicRmwSeqOp fix test fix rebae quirks * cleanup tests
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cranelift/codegen/src/isa/x64/inst/mod.rs

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@@ -30,6 +30,7 @@ use args::*;
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// Instructions (top level): definition
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// `Inst` is defined inside ISLE as `MInst`. We publicly re-export it here.
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pub use super::lower::isle::generated_code::AtomicRmwSeqOp;
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pub use super::lower::isle::generated_code::MInst as Inst;
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/// Out-of-line data for return-calls, to keep the size of `Inst` down.

cranelift/codegen/src/isa/x64/mod.rs

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//! X86_64-bit Instruction Set Architecture.
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pub use self::inst::{args, EmitInfo, EmitState, Inst};
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pub use self::inst::{args, AtomicRmwSeqOp, EmitInfo, EmitState, Inst};
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use super::{OwnedTargetIsa, TargetIsa};
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use crate::dominator_tree::DominatorTree;
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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i32)
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(i32.atomic.rmw16.and_u (i32.const 0) (i32.const 42))))
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;; wasm[0]::function[0]:
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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x10, %r11
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;; cmpq %rsp, %r11
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;; ja 0x72
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;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
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;; movl $0x2a, %eax
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;; movl $0, %ecx
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;; andw $1, %cx
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;; cmpw $0, %cx
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;; jne 0x74
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;; 44: movl $0, %ecx
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;; movq 0x58(%r14), %r11
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;; movq (%r11), %rdx
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;; addq %rcx, %rdx
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;; movzwq (%rdx), %rax
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;; movq %rax, %r11
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;; andq %rax, %r11
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;; lock cmpxchgw %r11w, (%rdx)
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;; jne 0x57
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;; 69: movzwl %ax, %eax
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;; addq $0x10, %rsp
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;; popq %rbp
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;; retq
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;; 72: ud2
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;; 74: ud2

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