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-23533
lines changed

9 files changed

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-23533
lines changed

‎source/fpga/fpga_application.h‎

Lines changed: 23571 additions & 23475 deletions
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‎source/fpga/modules/camera/testbenches/csi/source/csi/csi2_transmitter_ip/component.xml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -306,7 +306,7 @@
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</lsccip:deviceInfo>
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<lsccip:generationInfo>
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<lsccip:fileVersion>20180929</lsccip:fileVersion>
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<lsccip:createdTimestamp>2025 01 02 17:25:51</lsccip:createdTimestamp>
309+
<lsccip:createdTimestamp>2025 01 03 11:42:27</lsccip:createdTimestamp>
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<lsccip:radiantBuild>&quot;Lattice Radiant Software&quot; (64-bit) 2023.2.1.288.0</lsccip:radiantBuild>
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</lsccip:generationInfo>
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</ipxact:vendorExtensions>

‎source/fpga/modules/camera/testbenches/csi/source/csi/csi2_transmitter_ip/csi2_transmitter_ip.ipx‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,22 +1,22 @@
11
<?xml version="1.0" ?>
2-
<RadiantModule architecture="LIFCL" date="2025 01 02 17:25:51" device="LIFCL-17" gen_platform="Radiant" generator="ipgen" library="ip" module="dphy_tx" name="csi2_transmitter_ip" package="WLCSP72" source_format="Verilog" speed="8_Low-Power_1.0V" vendor="latticesemi.com" version="1.9.2">
2+
<RadiantModule architecture="LIFCL" date="2025 01 03 11:42:27" device="LIFCL-17" gen_platform="Radiant" generator="ipgen" library="ip" module="dphy_tx" name="csi2_transmitter_ip" package="WLCSP72" source_format="Verilog" speed="8_Low-Power_1.0V" vendor="latticesemi.com" version="1.9.2">
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<Package>
4-
<File modified="2025 01 02 17:25:51" name="rtl/csi2_transmitter_ip_bb.v" type="black_box_verilog"/>
5-
<File modified="2025 01 02 17:25:51" name="csi2_transmitter_ip.cfg" type="cfg"/>
6-
<File modified="2025 01 02 17:25:51" name="misc/csi2_transmitter_ip_tmpl.v" type="template_verilog"/>
7-
<File modified="2025 01 02 17:25:51" name="misc/csi2_transmitter_ip_tmpl.vhd" type="template_vhdl"/>
8-
<File modified="2025 01 02 17:25:51" name="rtl/csi2_transmitter_ip.v" type="top_level_verilog"/>
9-
<File modified="2025 01 02 17:25:51" name="constraints/csi2_transmitter_ip.ldc" type="timing_constraints"/>
10-
<File modified="2025 01 02 17:25:51" name="testbench/dut_params.v" type="dependency_file"/>
11-
<File modified="2025 01 02 17:25:51" name="testbench/dut_inst.v" type="dependency_file"/>
12-
<File modified="2025 01 02 17:25:51" name="eval/dut_params.v" type="dependency_file"/>
13-
<File modified="2025 01 02 17:25:51" name="eval/dut_inst.v" type="dependency_file"/>
14-
<File modified="2025 01 02 17:25:51" name="component.xml" type="IP-XACT_component"/>
15-
<File modified="2025 01 02 17:25:51" name="design.xml" type="IP-XACT_design"/>
4+
<File modified="2025 01 03 11:42:27" name="rtl/csi2_transmitter_ip_bb.v" type="black_box_verilog"/>
5+
<File modified="2025 01 03 11:42:27" name="csi2_transmitter_ip.cfg" type="cfg"/>
6+
<File modified="2025 01 03 11:42:27" name="misc/csi2_transmitter_ip_tmpl.v" type="template_verilog"/>
7+
<File modified="2025 01 03 11:42:27" name="misc/csi2_transmitter_ip_tmpl.vhd" type="template_vhdl"/>
8+
<File modified="2025 01 03 11:42:27" name="rtl/csi2_transmitter_ip.v" type="top_level_verilog"/>
9+
<File modified="2025 01 03 11:42:27" name="constraints/csi2_transmitter_ip.ldc" type="timing_constraints"/>
10+
<File modified="2025 01 03 11:42:27" name="testbench/dut_params.v" type="dependency_file"/>
11+
<File modified="2025 01 03 11:42:27" name="testbench/dut_inst.v" type="dependency_file"/>
12+
<File modified="2025 01 03 11:42:27" name="eval/dut_params.v" type="dependency_file"/>
13+
<File modified="2025 01 03 11:42:27" name="eval/dut_inst.v" type="dependency_file"/>
14+
<File modified="2025 01 03 11:42:27" name="component.xml" type="IP-XACT_component"/>
15+
<File modified="2025 01 03 11:42:27" name="design.xml" type="IP-XACT_design"/>
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<File modified="2023 12 21 13:48:31" name="testbench/lscc_dphy_tx_model.v" type="testbench_verilog"/>
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<File modified="2023 12 21 13:48:31" name="testbench/tb_top.v" type="testbench_verilog"/>
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<File modified="2023 12 21 13:48:31" name="testbench/rx_model.v" type="testbench_verilog"/>
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<File modified="2025 01 02 16:25:51" name="eval/constraint_for_lse.pdc" type="eval"/>
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<File modified="2025 01 02 16:25:51" name="eval/constraint_for_synp.pdc" type="eval"/>
19+
<File modified="2025 01 03 10:42:27" name="eval/constraint_for_lse.pdc" type="eval"/>
20+
<File modified="2025 01 03 10:42:27" name="eval/constraint_for_synp.pdc" type="eval"/>
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</Package>
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</RadiantModule>

‎source/fpga/modules/camera/testbenches/csi/source/csi/pixel_to_byte_ip/component.xml‎

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Original file line numberDiff line numberDiff line change
@@ -273,7 +273,7 @@
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</lsccip:deviceInfo>
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<lsccip:generationInfo>
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<lsccip:fileVersion>20180929</lsccip:fileVersion>
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<lsccip:createdTimestamp>2025 01 02 17:26:32</lsccip:createdTimestamp>
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<lsccip:createdTimestamp>2025 01 03 11:42:28</lsccip:createdTimestamp>
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<lsccip:radiantBuild>&quot;Lattice Radiant Software&quot; (64-bit) 2023.2.1.288.0</lsccip:radiantBuild>
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</lsccip:generationInfo>
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</ipxact:vendorExtensions>

‎source/fpga/modules/camera/testbenches/csi/source/csi/pixel_to_byte_ip/pixel_to_byte_ip.ipx‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,16 @@
11
<?xml version="1.0" ?>
2-
<RadiantModule architecture="LIFCL" date="2025 01 02 17:26:33" device="LIFCL-17" gen_platform="Radiant" generator="ipgen" library="ip" module="pixel2byte" name="pixel_to_byte_ip" package="WLCSP72" source_format="Verilog" speed="8_Low-Power_1.0V" vendor="latticesemi.com" version="1.5.0">
2+
<RadiantModule architecture="LIFCL" date="2025 01 03 11:42:28" device="LIFCL-17" gen_platform="Radiant" generator="ipgen" library="ip" module="pixel2byte" name="pixel_to_byte_ip" package="WLCSP72" source_format="Verilog" speed="8_Low-Power_1.0V" vendor="latticesemi.com" version="1.5.0">
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<Package>
4-
<File modified="2025 01 02 17:26:32" name="rtl/pixel_to_byte_ip_bb.v" type="black_box_verilog"/>
5-
<File modified="2025 01 02 17:26:32" name="pixel_to_byte_ip.cfg" type="cfg"/>
6-
<File modified="2025 01 02 17:26:32" name="misc/pixel_to_byte_ip_tmpl.v" type="template_verilog"/>
7-
<File modified="2025 01 02 17:26:32" name="misc/pixel_to_byte_ip_tmpl.vhd" type="template_vhdl"/>
8-
<File modified="2025 01 02 17:26:32" name="rtl/pixel_to_byte_ip.v" type="top_level_verilog"/>
9-
<File modified="2025 01 02 17:26:32" name="constraints/pixel_to_byte_ip.ldc" type="timing_constraints"/>
10-
<File modified="2025 01 02 17:26:32" name="testbench/dut_params.v" type="dependency_file"/>
11-
<File modified="2025 01 02 17:26:32" name="testbench/dut_inst.v" type="dependency_file"/>
12-
<File modified="2025 01 02 17:26:32" name="component.xml" type="IP-XACT_component"/>
13-
<File modified="2025 01 02 17:26:32" name="design.xml" type="IP-XACT_design"/>
4+
<File modified="2025 01 03 11:42:27" name="rtl/pixel_to_byte_ip_bb.v" type="black_box_verilog"/>
5+
<File modified="2025 01 03 11:42:27" name="pixel_to_byte_ip.cfg" type="cfg"/>
6+
<File modified="2025 01 03 11:42:27" name="misc/pixel_to_byte_ip_tmpl.v" type="template_verilog"/>
7+
<File modified="2025 01 03 11:42:27" name="misc/pixel_to_byte_ip_tmpl.vhd" type="template_vhdl"/>
8+
<File modified="2025 01 03 11:42:28" name="rtl/pixel_to_byte_ip.v" type="top_level_verilog"/>
9+
<File modified="2025 01 03 11:42:28" name="constraints/pixel_to_byte_ip.ldc" type="timing_constraints"/>
10+
<File modified="2025 01 03 11:42:28" name="testbench/dut_params.v" type="dependency_file"/>
11+
<File modified="2025 01 03 11:42:28" name="testbench/dut_inst.v" type="dependency_file"/>
12+
<File modified="2025 01 03 11:42:28" name="component.xml" type="IP-XACT_component"/>
13+
<File modified="2025 01 03 11:42:28" name="design.xml" type="IP-XACT_design"/>
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<File modified="2023 02 21 09:56:05" name="testbench/tb_top.v" type="testbench_verilog"/>
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<File modified="2023 02 21 09:56:05" name="testbench/create_defines.py" type="testbench"/>
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<File modified="2023 02 21 09:56:05" name="testbench/tb_include/test_snow_pixel2byte_dsi_reset.vh" type="testbench"/>
@@ -21,6 +21,6 @@
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<File modified="2023 02 21 09:56:05" name="testbench/tb_include/test_snow_pixel2byte_dsi_trans.vh" type="testbench"/>
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<File modified="2023 02 21 09:56:05" name="testbench/vid_timing_gen_driver.v" type="testbench_verilog"/>
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<File modified="2023 02 21 09:56:05" name="testbench/byte_out_monitor.v" type="testbench_verilog"/>
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<File modified="2025 01 02 16:26:33" name="testbench/dut_defines.v" type="testbench_verilog"/>
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<File modified="2025 01 03 10:42:28" name="testbench/dut_defines.v" type="testbench_verilog"/>
2525
</Package>
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</RadiantModule>

‎source/fpga/radiant/byte_to_pixel_ip/byte_to_pixel_ip.ipx‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,22 +1,22 @@
11
<?xml version="1.0" ?>
2-
<RadiantModule architecture="LIFCL" date="2024 04 16 16:25:08" device="LIFCL-17" gen_platform="Radiant" generator="ipgen" library="ip" module="byte2pixel" name="byte_to_pixel_ip" package="WLCSP72" source_format="Verilog" speed="8_Low-Power_1.0V" vendor="latticesemi.com" version="1.6.1">
2+
<RadiantModule architecture="LIFCL" date="2025 01 03 11:42:26" device="LIFCL-17" gen_platform="Radiant" generator="ipgen" library="ip" module="byte2pixel" name="byte_to_pixel_ip" package="WLCSP72" source_format="Verilog" speed="8_Low-Power_1.0V" vendor="latticesemi.com" version="1.6.1">
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<Package>
4-
<File modified="2024 04 16 16:25:08" name="rtl/byte_to_pixel_ip_bb.v" type="black_box_verilog"/>
5-
<File modified="2024 04 16 16:25:08" name="byte_to_pixel_ip.cfg" type="cfg"/>
6-
<File modified="2024 04 16 16:25:08" name="misc/byte_to_pixel_ip_tmpl.v" type="template_verilog"/>
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<File modified="2024 04 16 16:25:08" name="misc/byte_to_pixel_ip_tmpl.vhd" type="template_vhdl"/>
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<File modified="2024 04 16 16:25:08" name="rtl/byte_to_pixel_ip.v" type="top_level_verilog"/>
9-
<File modified="2024 04 16 16:25:08" name="constraints/byte_to_pixel_ip.ldc" type="timing_constraints"/>
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<File modified="2024 04 16 16:25:08" name="testbench/dut_params.v" type="dependency_file"/>
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<File modified="2024 04 16 16:25:08" name="testbench/dut_inst.v" type="dependency_file"/>
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<File modified="2024 04 16 16:25:08" name="eval/dut_params.v" type="dependency_file"/>
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<File modified="2024 04 16 16:25:08" name="eval/dut_inst.v" type="dependency_file"/>
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<File modified="2024 04 16 16:25:08" name="component.xml" type="IP-XACT_component"/>
15-
<File modified="2024 04 16 16:25:08" name="design.xml" type="IP-XACT_design"/>
4+
<File modified="2025 01 03 11:42:26" name="rtl/byte_to_pixel_ip_bb.v" type="black_box_verilog"/>
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<File modified="2025 01 03 11:42:26" name="byte_to_pixel_ip.cfg" type="cfg"/>
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<File modified="2025 01 03 11:42:26" name="misc/byte_to_pixel_ip_tmpl.v" type="template_verilog"/>
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<File modified="2025 01 03 11:42:26" name="misc/byte_to_pixel_ip_tmpl.vhd" type="template_vhdl"/>
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<File modified="2025 01 03 11:42:26" name="rtl/byte_to_pixel_ip.v" type="top_level_verilog"/>
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<File modified="2025 01 03 11:42:26" name="constraints/byte_to_pixel_ip.ldc" type="timing_constraints"/>
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<File modified="2025 01 03 11:42:26" name="testbench/dut_params.v" type="dependency_file"/>
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<File modified="2025 01 03 11:42:26" name="testbench/dut_inst.v" type="dependency_file"/>
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<File modified="2025 01 03 11:42:26" name="eval/dut_params.v" type="dependency_file"/>
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<File modified="2025 01 03 11:42:26" name="eval/dut_inst.v" type="dependency_file"/>
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<File modified="2025 01 03 11:42:26" name="component.xml" type="IP-XACT_component"/>
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<File modified="2025 01 03 11:42:26" name="design.xml" type="IP-XACT_design"/>
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<File modified="2023 11 30 23:42:35" name="testbench/pixel_monitor.v" type="testbench_verilog"/>
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<File modified="2023 11 30 23:42:35" name="testbench/tb_top.v" type="testbench_verilog"/>
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<File modified="2023 11 30 23:42:35" name="testbench/byte_driver.v" type="testbench_verilog"/>
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<File modified="2024 04 16 14:25:08" name="eval/constraint.pdc" type="eval"/>
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<File modified="2025 01 03 10:42:26" name="eval/constraint.pdc" type="eval"/>
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<File modified="2023 11 30 23:42:35" name="eval/ip_tmp_eval.pdc" type="eval"/>
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</Package>
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</RadiantModule>

‎source/fpga/radiant/byte_to_pixel_ip/component.xml‎

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Original file line numberDiff line numberDiff line change
@@ -255,7 +255,7 @@
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</lsccip:deviceInfo>
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<lsccip:generationInfo>
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<lsccip:fileVersion>20180929</lsccip:fileVersion>
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<lsccip:createdTimestamp>2024 04 16 16:25:08</lsccip:createdTimestamp>
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<lsccip:createdTimestamp>2025 01 03 11:42:26</lsccip:createdTimestamp>
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<lsccip:radiantBuild>&quot;Lattice Radiant Software&quot; (64-bit) 2023.2.1.288.0</lsccip:radiantBuild>
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</lsccip:generationInfo>
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</ipxact:vendorExtensions>

‎source/fpga/radiant/csi2_receiver_ip/component.xml‎

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Original file line numberDiff line numberDiff line change
@@ -467,7 +467,7 @@
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</lsccip:deviceInfo>
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<lsccip:generationInfo>
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<lsccip:fileVersion>20180929</lsccip:fileVersion>
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<lsccip:createdTimestamp>2024 04 16 16:25:08</lsccip:createdTimestamp>
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<lsccip:createdTimestamp>2025 01 03 11:42:27</lsccip:createdTimestamp>
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<lsccip:radiantBuild>&quot;Lattice Radiant Software&quot; (64-bit) 2023.2.1.288.0</lsccip:radiantBuild>
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</lsccip:generationInfo>
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</ipxact:vendorExtensions>

‎source/fpga/radiant/csi2_receiver_ip/csi2_receiver_ip.ipx‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,18 @@
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<?xml version="1.0" ?>
2-
<RadiantModule architecture="LIFCL" date="2024 04 16 16:25:08" device="LIFCL-17" gen_platform="Radiant" generator="ipgen" library="ip" module="dphy_rx" name="csi2_receiver_ip" package="WLCSP72" source_format="Verilog" speed="8_Low-Power_1.0V" vendor="latticesemi.com" version="1.6.1">
2+
<RadiantModule architecture="LIFCL" date="2025 01 03 11:42:27" device="LIFCL-17" gen_platform="Radiant" generator="ipgen" library="ip" module="dphy_rx" name="csi2_receiver_ip" package="WLCSP72" source_format="Verilog" speed="8_Low-Power_1.0V" vendor="latticesemi.com" version="1.6.1">
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<Package>
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<File modified="2024 04 16 16:25:08" name="rtl/csi2_receiver_ip_bb.v" type="black_box_verilog"/>
5-
<File modified="2024 04 16 16:25:08" name="csi2_receiver_ip.cfg" type="cfg"/>
6-
<File modified="2024 04 16 16:25:08" name="misc/csi2_receiver_ip_tmpl.v" type="template_verilog"/>
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<File modified="2024 04 16 16:25:08" name="misc/csi2_receiver_ip_tmpl.vhd" type="template_vhdl"/>
8-
<File modified="2024 04 16 16:25:08" name="rtl/csi2_receiver_ip.v" type="top_level_verilog"/>
9-
<File modified="2024 04 16 16:25:08" name="constraints/csi2_receiver_ip.ldc" type="timing_constraints"/>
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<File modified="2024 04 16 16:25:08" name="testbench/dut_params.v" type="dependency_file"/>
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<File modified="2024 04 16 16:25:08" name="testbench/dut_inst.v" type="dependency_file"/>
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<File modified="2024 04 16 16:25:08" name="eval/dut_params.v" type="dependency_file"/>
13-
<File modified="2024 04 16 16:25:08" name="eval/dut_inst.v" type="dependency_file"/>
14-
<File modified="2024 04 16 16:25:08" name="component.xml" type="IP-XACT_component"/>
15-
<File modified="2024 04 16 16:25:08" name="design.xml" type="IP-XACT_design"/>
4+
<File modified="2025 01 03 11:42:27" name="rtl/csi2_receiver_ip_bb.v" type="black_box_verilog"/>
5+
<File modified="2025 01 03 11:42:27" name="csi2_receiver_ip.cfg" type="cfg"/>
6+
<File modified="2025 01 03 11:42:27" name="misc/csi2_receiver_ip_tmpl.v" type="template_verilog"/>
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<File modified="2025 01 03 11:42:27" name="misc/csi2_receiver_ip_tmpl.vhd" type="template_vhdl"/>
8+
<File modified="2025 01 03 11:42:27" name="rtl/csi2_receiver_ip.v" type="top_level_verilog"/>
9+
<File modified="2025 01 03 11:42:27" name="constraints/csi2_receiver_ip.ldc" type="timing_constraints"/>
10+
<File modified="2025 01 03 11:42:27" name="testbench/dut_params.v" type="dependency_file"/>
11+
<File modified="2025 01 03 11:42:27" name="testbench/dut_inst.v" type="dependency_file"/>
12+
<File modified="2025 01 03 11:42:27" name="eval/dut_params.v" type="dependency_file"/>
13+
<File modified="2025 01 03 11:42:27" name="eval/dut_inst.v" type="dependency_file"/>
14+
<File modified="2025 01 03 11:42:27" name="component.xml" type="IP-XACT_component"/>
15+
<File modified="2025 01 03 11:42:27" name="design.xml" type="IP-XACT_design"/>
1616
<File modified="2023 12 21 13:26:15" name="testbench/tb_top.sv" type="testbench_system_verilog"/>
1717
<File modified="2023 12 21 13:26:15" name="testbench/clk_driver.sv" type="testbench_system_verilog"/>
1818
<File modified="2023 12 21 13:26:15" name="testbench/csi2_model.sv" type="testbench_system_verilog"/>

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