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KVM: TDX: Add accessors VMX VMCS helpers
JIRA: https://issues.redhat.com/browse/RHEL-15711 Upstream status: https://git.kernel.org/pub/scm/virt/kvm/kvm.git TDX defines SEAMCALL APIs to access TDX control structures corresponding to the VMX VMCS. Introduce helper accessors to hide its SEAMCALL ABI details. Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Co-developed-by: Rick Edgecombe <rick.p.edgecombe@intel.com> Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com> Co-developed-by: Yan Zhao <yan.y.zhao@intel.com> Signed-off-by: Yan Zhao <yan.y.zhao@intel.com> Message-ID: <20241112073551.22070-1-yan.y.zhao@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> (cherry picked from commit fe1e6d4) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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‎arch/x86/kvm/vmx/tdx.c‎

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@@ -36,6 +36,19 @@ static enum cpuhp_state tdx_cpuhp_state;
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static const struct tdx_sys_info *tdx_sysinfo;
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void tdh_vp_rd_failed(struct vcpu_tdx *tdx, char *uclass, u32 field, u64 err)
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{
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KVM_BUG_ON(1, tdx->vcpu.kvm);
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pr_err("TDH_VP_RD[%s.0x%x] failed 0x%llx\n", uclass, field, err);
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}
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void tdh_vp_wr_failed(struct vcpu_tdx *tdx, char *uclass, char *op, u32 field,
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u64 val, u64 err)
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{
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KVM_BUG_ON(1, tdx->vcpu.kvm);
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pr_err("TDH_VP_WR[%s.0x%x]%s0x%llx failed: 0x%llx\n", uclass, field, op, val, err);
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}
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#define KVM_SUPPORTED_TD_ATTRS (TDX_TD_ATTR_SEPT_VE_DISABLE)
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static __always_inline struct kvm_tdx *to_kvm_tdx(struct kvm *kvm)

‎arch/x86/kvm/vmx/tdx.h‎

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Original file line numberDiff line numberDiff line change
@@ -48,6 +48,10 @@ struct vcpu_tdx {
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enum vcpu_tdx_state state;
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};
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void tdh_vp_rd_failed(struct vcpu_tdx *tdx, char *uclass, u32 field, u64 err);
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void tdh_vp_wr_failed(struct vcpu_tdx *tdx, char *uclass, char *op, u32 field,
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u64 val, u64 err);
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static inline bool is_td(struct kvm *kvm)
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{
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return kvm->arch.vm_type == KVM_X86_TDX_VM;
@@ -69,6 +73,90 @@ static __always_inline u64 td_tdcs_exec_read64(struct kvm_tdx *kvm_tdx, u32 fiel
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}
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return data;
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}
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static __always_inline void tdvps_vmcs_check(u32 field, u8 bits)
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{
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#define VMCS_ENC_ACCESS_TYPE_MASK 0x1UL
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#define VMCS_ENC_ACCESS_TYPE_FULL 0x0UL
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#define VMCS_ENC_ACCESS_TYPE_HIGH 0x1UL
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#define VMCS_ENC_ACCESS_TYPE(field) ((field) & VMCS_ENC_ACCESS_TYPE_MASK)
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/* TDX is 64bit only. HIGH field isn't supported. */
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) &&
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VMCS_ENC_ACCESS_TYPE(field) == VMCS_ENC_ACCESS_TYPE_HIGH,
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"Read/Write to TD VMCS *_HIGH fields not supported");
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BUILD_BUG_ON(bits != 16 && bits != 32 && bits != 64);
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#define VMCS_ENC_WIDTH_MASK GENMASK(14, 13)
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#define VMCS_ENC_WIDTH_16BIT (0UL << 13)
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#define VMCS_ENC_WIDTH_64BIT (1UL << 13)
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#define VMCS_ENC_WIDTH_32BIT (2UL << 13)
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#define VMCS_ENC_WIDTH_NATURAL (3UL << 13)
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#define VMCS_ENC_WIDTH(field) ((field) & VMCS_ENC_WIDTH_MASK)
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/* TDX is 64bit only. i.e. natural width = 64bit. */
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BUILD_BUG_ON_MSG(bits != 64 && __builtin_constant_p(field) &&
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(VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_64BIT ||
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VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_NATURAL),
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"Invalid TD VMCS access for 64-bit field");
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BUILD_BUG_ON_MSG(bits != 32 && __builtin_constant_p(field) &&
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VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_32BIT,
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"Invalid TD VMCS access for 32-bit field");
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BUILD_BUG_ON_MSG(bits != 16 && __builtin_constant_p(field) &&
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VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_16BIT,
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"Invalid TD VMCS access for 16-bit field");
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}
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#define TDX_BUILD_TDVPS_ACCESSORS(bits, uclass, lclass) \
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static __always_inline u##bits td_##lclass##_read##bits(struct vcpu_tdx *tdx, \
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u32 field) \
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{ \
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u64 err, data; \
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\
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tdvps_##lclass##_check(field, bits); \
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err = tdh_vp_rd(&tdx->vp, TDVPS_##uclass(field), &data); \
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if (unlikely(err)) { \
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tdh_vp_rd_failed(tdx, #uclass, field, err); \
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return 0; \
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} \
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return (u##bits)data; \
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} \
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static __always_inline void td_##lclass##_write##bits(struct vcpu_tdx *tdx, \
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u32 field, u##bits val) \
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{ \
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u64 err; \
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\
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tdvps_##lclass##_check(field, bits); \
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err = tdh_vp_wr(&tdx->vp, TDVPS_##uclass(field), val, \
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GENMASK_ULL(bits - 1, 0)); \
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if (unlikely(err)) \
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tdh_vp_wr_failed(tdx, #uclass, " = ", field, (u64)val, err); \
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} \
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static __always_inline void td_##lclass##_setbit##bits(struct vcpu_tdx *tdx, \
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u32 field, u64 bit) \
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{ \
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u64 err; \
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\
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tdvps_##lclass##_check(field, bits); \
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err = tdh_vp_wr(&tdx->vp, TDVPS_##uclass(field), bit, bit); \
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if (unlikely(err)) \
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tdh_vp_wr_failed(tdx, #uclass, " |= ", field, bit, err); \
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} \
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static __always_inline void td_##lclass##_clearbit##bits(struct vcpu_tdx *tdx, \
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u32 field, u64 bit) \
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{ \
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u64 err; \
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\
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tdvps_##lclass##_check(field, bits); \
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err = tdh_vp_wr(&tdx->vp, TDVPS_##uclass(field), 0, bit); \
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if (unlikely(err)) \
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tdh_vp_wr_failed(tdx, #uclass, " &= ~", field, bit, err);\
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}
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TDX_BUILD_TDVPS_ACCESSORS(16, VMCS, vmcs);
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TDX_BUILD_TDVPS_ACCESSORS(32, VMCS, vmcs);
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TDX_BUILD_TDVPS_ACCESSORS(64, VMCS, vmcs);
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#else
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static inline int tdx_bringup(void) { return 0; }
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static inline void tdx_cleanup(void) {}

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