@@ -1276,23 +1276,12 @@ int sdw_configure_dpn_intr(struct sdw_slave *slave,
12761276 return ret ;
12771277}
12781278
1279- static int sdw_slave_set_frequency (struct sdw_slave * slave )
1279+ int sdw_slave_get_scale_index (struct sdw_slave * slave , u8 * base )
12801280{
12811281 u32 mclk_freq = slave -> bus -> prop .mclk_freq ;
12821282 u32 curr_freq = slave -> bus -> params .curr_dr_freq >> 1 ;
12831283 unsigned int scale ;
12841284 u8 scale_index ;
1285- u8 base ;
1286- int ret ;
1287-
1288- /*
1289- * frequency base and scale registers are required for SDCA
1290- * devices. They may also be used for 1.2+/non-SDCA devices.
1291- * Driver can set the property, we will need a DisCo property
1292- * to discover this case from platform firmware.
1293- */
1294- if (!slave -> id .class_id && !slave -> prop .clock_reg_supported )
1295- return 0 ;
12961285
12971286 if (!mclk_freq ) {
12981287 dev_err (& slave -> dev ,
@@ -1311,19 +1300,19 @@ static int sdw_slave_set_frequency(struct sdw_slave *slave)
13111300 */
13121301 if (!(19200000 % mclk_freq )) {
13131302 mclk_freq = 19200000 ;
1314- base = SDW_SCP_BASE_CLOCK_19200000_HZ ;
1303+ * base = SDW_SCP_BASE_CLOCK_19200000_HZ ;
13151304 } else if (!(22579200 % mclk_freq )) {
13161305 mclk_freq = 22579200 ;
1317- base = SDW_SCP_BASE_CLOCK_22579200_HZ ;
1306+ * base = SDW_SCP_BASE_CLOCK_22579200_HZ ;
13181307 } else if (!(24576000 % mclk_freq )) {
13191308 mclk_freq = 24576000 ;
1320- base = SDW_SCP_BASE_CLOCK_24576000_HZ ;
1309+ * base = SDW_SCP_BASE_CLOCK_24576000_HZ ;
13211310 } else if (!(32000000 % mclk_freq )) {
13221311 mclk_freq = 32000000 ;
1323- base = SDW_SCP_BASE_CLOCK_32000000_HZ ;
1312+ * base = SDW_SCP_BASE_CLOCK_32000000_HZ ;
13241313 } else if (!(96000000 % mclk_freq )) {
13251314 mclk_freq = 24000000 ;
1326- base = SDW_SCP_BASE_CLOCK_24000000_HZ ;
1315+ * base = SDW_SCP_BASE_CLOCK_24000000_HZ ;
13271316 } else {
13281317 dev_err (& slave -> dev ,
13291318 "Unsupported clock base, mclk %d\n" ,
@@ -1354,6 +1343,34 @@ static int sdw_slave_set_frequency(struct sdw_slave *slave)
13541343 }
13551344 scale_index ++ ;
13561345
1346+ dev_dbg (& slave -> dev ,
1347+ "Configured bus base %d, scale %d, mclk %d, curr_freq %d\n" ,
1348+ * base , scale_index , mclk_freq , curr_freq );
1349+
1350+ return scale_index ;
1351+ }
1352+ EXPORT_SYMBOL (sdw_slave_get_scale_index );
1353+
1354+ static int sdw_slave_set_frequency (struct sdw_slave * slave )
1355+ {
1356+ int scale_index ;
1357+ u8 base ;
1358+ int ret ;
1359+
1360+ /*
1361+ * frequency base and scale registers are required for SDCA
1362+ * devices. They may also be used for 1.2+/non-SDCA devices.
1363+ * Driver can set the property directly, for now there's no
1364+ * DisCo property to discover support for the scaling registers
1365+ * from platform firmware.
1366+ */
1367+ if (!slave -> id .class_id && !slave -> prop .clock_reg_supported )
1368+ return 0 ;
1369+
1370+ scale_index = sdw_slave_get_scale_index (slave , & base );
1371+ if (scale_index < 0 )
1372+ return scale_index ;
1373+
13571374 ret = sdw_write_no_pm (slave , SDW_SCP_BUS_CLOCK_BASE , base );
13581375 if (ret < 0 ) {
13591376 dev_err (& slave -> dev ,
@@ -1373,10 +1390,6 @@ static int sdw_slave_set_frequency(struct sdw_slave *slave)
13731390 dev_err (& slave -> dev ,
13741391 "SDW_SCP_BUSCLOCK_SCALE_B1 write failed:%d\n" , ret );
13751392
1376- dev_dbg (& slave -> dev ,
1377- "Configured bus base %d, scale %d, mclk %d, curr_freq %d\n" ,
1378- base , scale_index , mclk_freq , curr_freq );
1379-
13801393 return ret ;
13811394}
13821395
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