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Merge tag 'coresight-next-v6.15' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next
Suzuki writes: coresight: updates for Linux v6.15 CoreSight self-hosted tracing driver subsystem update for Linux v6.15. The update includes: - CoreSight trace capture for Panic/Watchdog timeouts - Fixes to ETM4x driver to synchronize register reads as required by the TRM - Support for Qualcomm CoreSight TMC Control Unit driver - Conversion of device locks to raw_spinlock for components that are used by the Perf mode. - Miscellaneous fixes for the subsystem Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> * tag 'coresight-next-v6.15' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux: (41 commits) Coresight: Fix a NULL vs IS_ERR() bug in probe coresight: configfs: Constify struct config_item_type coresight: docs: Remove target sink from examples coresight/ultrasoc: change smb_drv_data spinlock's type to raw_spinlock_t coresight-tmc: change tmc_drvdata spinlock's type to raw_spinlock_t coresight-replicator: change replicator_drvdata spinlock's type to raw_spinlock_t coresight-funnel: change funnel_drvdata spinlock's type to raw_spinlock_t coresight-etb10: change etb_drvdata spinlock's type to raw_spinlock_t coresight-cti: change cti_drvdata spinlock's type to raw_spinlock_t coresight: change coresight_trace_id_map's lock type to raw_spinlock_t coresight-etm4x: change etmv4_drvdata spinlock type to raw_spinlock_t coresight: change coresight_device lock type to raw_spinlock_t coresight: add verification process for coresight_etm_get_trace_id Coresight: Add Coresight TMC Control Unit driver dt-bindings: arm: Add Coresight TMC Control Unit hardware Coresight: Change functions to accept the coresight_path Coresight: Change to read the trace ID from coresight_path Coresight: Allocate trace ID after building the path Coresight: Introduce a new struct coresight_path Coresight: Use coresight_etm_get_trace_id() in traceid_show() ...
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‎Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm‎

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@@ -257,3 +257,18 @@ Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_t
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Description:
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(RW) Set/Get the MSR(mux select register) for the CMB subunit
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TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_trig_lane
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Date: Feb 2025
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KernelVersion 6.15
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get which lane participates in the output pattern
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match cross trigger mechanism for the MCMB subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_lanes_select
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Date: Feb 2025
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KernelVersion 6.15
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the enablement of the individual lane.

‎Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml‎

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and ETF configurations.
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$ref: /schemas/graph.yaml#/properties/port
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memory-region:
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items:
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- description: Reserved trace buffer memory for ETR and ETF sinks.
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For ETR, this reserved memory region is used for trace data capture.
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Same region is used for trace data retention as well after a panic
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or watchdog reset.
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This reserved memory region is used as trace buffer or used for trace
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data retention only if specifically selected by the user in sysfs
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interface.
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The default memory usage models for ETR in sysfs/perf modes are
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otherwise unaltered.
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For ETF, this reserved memory region is used by default for
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retention of trace data synced from internal SRAM after a panic
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or watchdog reset.
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- description: Reserved meta data memory. Used for ETR and ETF sinks
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for storing metadata.
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memory-region-names:
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items:
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- const: tracedata
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- const: metadata
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required:
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- compatible
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- reg
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etr@20070000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x20070000 0x1000>;
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memory-region = <&etr_trace_mem_reserved>,
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<&etr_mdata_mem_reserved>;
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memory-region-names = "tracedata", "metadata";
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";

‎Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: CoreSight TMC Control Unit
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maintainers:
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- Yuanfang Zhang <quic_yuanfang@quicinc.com>
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- Mao Jinlong <quic_jinlmao@quicinc.com>
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- Jie Gan <quic_jiegan@quicinc.com>
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description: |
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The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB),
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Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configurations.
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The configuration mode (ETB, ETF, ETR) is discovered at boot time when
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the device is probed.
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The Coresight TMC Control unit controls various Coresight behaviors.
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It works as a helper device when connected to TMC ETR device.
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It is responsible for controlling the data filter function based on
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the source device's Trace ID for TMC ETR device. The trace data with
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that Trace id can get into ETR's buffer while other trace data gets
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ignored.
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properties:
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compatible:
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enum:
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- qcom,sa8775p-ctcu
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: apb
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in-ports:
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$ref: /schemas/graph.yaml#/properties/ports
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patternProperties:
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'^port(@[0-1])?$':
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description: Input connections from CoreSight Trace bus
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$ref: /schemas/graph.yaml#/properties/port
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required:
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- compatible
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- reg
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- in-ports
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additionalProperties: false
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examples:
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- |
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ctcu@1001000 {
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compatible = "qcom,sa8775p-ctcu";
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reg = <0x1001000 0x1000>;
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clocks = <&aoss_qmp>;
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clock-names = "apb";
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ctcu_in_port0: endpoint {
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remote-endpoint = <&etr0_out_port>;
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};
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};
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port@1 {
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reg = <1>;
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ctcu_in_port1: endpoint {
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remote-endpoint = <&etr1_out_port>;
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};
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};
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};
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};

‎Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml‎

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- const: arm,primecell
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reg:
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minItems: 1
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maxItems: 2
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maxItems: 1
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clocks:
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maxItems: 1

‎Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml‎

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- const: arm,primecell
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reg:
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minItems: 1
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maxItems: 2
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maxItems: 1
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qcom,dsb-element-bits:
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description:

‎Documentation/trace/coresight/coresight.rst‎

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cs_etm// [Kernel PMU event]
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linaro@linaro-nano:~$
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Regardless of the number of tracers available in a system (usually equal to the
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amount of processor cores), the "cs_etm" PMU will be listed only once.
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A Coresight PMU works the same way as any other PMU, i.e the name of the PMU is
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listed along with configuration options within forward slashes '/'. Since a
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Coresight system will typically have more than one sink, the name of the sink to
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work with needs to be specified as an event option.
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On newer kernels the available sinks are listed in sysFS under
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provided along with configuration options within forward slashes '/' (see
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`Config option formats`_).
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Advanced Perf framework usage
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-----------------------------
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Sink selection
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~~~~~~~~~~~~~~
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An appropriate sink will be selected automatically for use with Perf, but since
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there will typically be more than one sink, the name of the sink to use may be
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specified as a special config option prefixed with '@'.
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The available sinks are listed in sysFS under
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($SYSFS)/bus/event_source/devices/cs_etm/sinks/::
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root@localhost:/sys/bus/event_source/devices/cs_etm/sinks# ls
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tmc_etf0 tmc_etr0 tpiu0
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On older kernels, this may need to be found from the list of coresight devices,
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available under ($SYSFS)/bus/coresight/devices/::
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root:~# ls /sys/bus/coresight/devices/
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etm0 etm1 etm2 etm3 etm4 etm5 funnel0
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funnel1 funnel2 replicator0 stm0 tmc_etf0 tmc_etr0 tpiu0
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root@linaro-nano:~# perf record -e cs_etm/@tmc_etr0/u --per-thread program
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As mentioned above in section "Device Naming scheme", the names of the devices could
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look different from what is used in the example above. One must use the device names
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as it appears under the sysFS.
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The syntax within the forward slashes '/' is important. The '@' character
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tells the parser that a sink is about to be specified and that this is the sink
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to use for the trace session.
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More information on the above and other example on how to use Coresight with
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the perf tools can be found in the "HOWTO.md" file of the openCSD gitHub
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repository [#third]_.
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Advanced perf framework usage
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-----------------------------
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AutoFDO analysis using the perf tools
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Execution can be recorded using 'perf record' with the cs_etm event,
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specifying the name of the sink to record to, e.g::
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perf record -e cs_etm/@tmc_etr0/u --per-thread
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perf record -e cs_etm//u --per-thread
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The 'perf report' and 'perf script' commands can be used to analyze execution,
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synthesizing instruction and branch events from the instruction trace.
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Bubble sorting array of 30000 elements
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5910 ms
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$ perf record -e cs_etm/@tmc_etr0/u --per-thread taskset -c 2 ./sort
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$ perf record -e cs_etm//u --per-thread taskset -c 2 ./sort
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Bubble sorting array of 30000 elements
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12543 ms
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[ perf record: Woken up 35 times to write data ]

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