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crypto: qat - enable deflate for QAT GEN4
jira LE-1907 Rebuild_History Non-Buildable kernel-5.14.0-284.30.1.el9_2 commit-author Giovanni Cabiddu <giovanni.cabiddu@intel.com> commit 5b14b2b Enable deflate for QAT GEN4 devices. This adds (1) logic to create configuration entries at probe time for the compression instances for QAT GEN4 devices; (2) the implementation of QAT GEN4 specific compression operations, required since the creation of the compression request template is different between GEN2 and GEN4; and (3) updates to the firmware API related to compression for GEN4. The implementation configures the device to produce data compressed dynamically, optimized for throughput over compression ratio. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Adam Guerin <adam.guerin@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> (cherry picked from commit 5b14b2b) Signed-off-by: Jonathan Maple <jmaple@ciq.com>
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8 files changed

+689
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lines changed

‎drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
#include <adf_accel_devices.h>
55
#include <adf_cfg.h>
66
#include <adf_common_drv.h>
7+
#include <adf_gen4_dc.h>
78
#include <adf_gen4_hw_data.h>
89
#include <adf_gen4_pfvf.h>
910
#include <adf_gen4_pm.h>
@@ -357,10 +358,11 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data)
357358
hw_data->ring_pair_reset = adf_gen4_ring_pair_reset;
358359
hw_data->enable_pm = adf_gen4_enable_pm;
359360
hw_data->handle_pm_interrupt = adf_gen4_handle_pm_interrupt;
360-
hw_data->dev_config = adf_crypto_dev_config;
361+
hw_data->dev_config = adf_gen4_dev_config;
361362

362363
adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);
363364
adf_gen4_init_pf_pfvf_ops(&hw_data->pfvf_ops);
365+
adf_gen4_init_dc_ops(&hw_data->dc_ops);
364366
}
365367

366368
void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data)

‎drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,6 @@ enum icp_qat_4xxx_slice_mask {
7070

7171
void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data);
7272
void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data);
73-
int adf_crypto_dev_config(struct adf_accel_dev *accel_dev);
73+
int adf_gen4_dev_config(struct adf_accel_dev *accel_dev);
7474

7575
#endif

‎drivers/crypto/qat/qat_4xxx/adf_drv.c‎

Lines changed: 127 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include <adf_common_drv.h>
1010

1111
#include "adf_4xxx_hw_data.h"
12+
#include "qat_compression.h"
1213
#include "qat_crypto.h"
1314
#include "adf_transport_access_macros.h"
1415

@@ -19,6 +20,16 @@ static const struct pci_device_id adf_pci_tbl[] = {
1920
};
2021
MODULE_DEVICE_TABLE(pci, adf_pci_tbl);
2122

23+
enum configs {
24+
DEV_CFG_CY = 0,
25+
DEV_CFG_DC,
26+
};
27+
28+
static const char * const services_operations[] = {
29+
ADF_CFG_CY,
30+
ADF_CFG_DC,
31+
};
32+
2233
static void adf_cleanup_accel(struct adf_accel_dev *accel_dev)
2334
{
2435
if (accel_dev->hw_device) {
@@ -53,7 +64,7 @@ static int adf_cfg_dev_init(struct adf_accel_dev *accel_dev)
5364
return 0;
5465
}
5566

56-
int adf_crypto_dev_config(struct adf_accel_dev *accel_dev)
67+
static int adf_crypto_dev_config(struct adf_accel_dev *accel_dev)
5768
{
5869
char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES];
5970
int banks = GET_MAX_BANKS(accel_dev);
@@ -68,14 +79,6 @@ int adf_crypto_dev_config(struct adf_accel_dev *accel_dev)
6879
else
6980
instances = 0;
7081

71-
ret = adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC);
72-
if (ret)
73-
goto err;
74-
75-
ret = adf_cfg_section_add(accel_dev, "Accelerator0");
76-
if (ret)
77-
goto err;
78-
7982
for (i = 0; i < instances; i++) {
8083
val = i;
8184
bank = i * 2;
@@ -161,10 +164,122 @@ int adf_crypto_dev_config(struct adf_accel_dev *accel_dev)
161164
if (ret)
162165
goto err;
163166

164-
set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status);
165167
return 0;
166168
err:
167-
dev_err(&GET_DEV(accel_dev), "Failed to start QAT accel dev\n");
169+
dev_err(&GET_DEV(accel_dev), "Failed to add configuration for crypto\n");
170+
return ret;
171+
}
172+
173+
static int adf_comp_dev_config(struct adf_accel_dev *accel_dev)
174+
{
175+
char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES];
176+
int banks = GET_MAX_BANKS(accel_dev);
177+
int cpus = num_online_cpus();
178+
unsigned long val;
179+
int instances;
180+
int ret;
181+
int i;
182+
183+
if (adf_hw_dev_has_compression(accel_dev))
184+
instances = min(cpus, banks);
185+
else
186+
instances = 0;
187+
188+
for (i = 0; i < instances; i++) {
189+
val = i;
190+
snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_BANK_NUM, i);
191+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
192+
key, &val, ADF_DEC);
193+
if (ret)
194+
goto err;
195+
196+
val = 512;
197+
snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_SIZE, i);
198+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
199+
key, &val, ADF_DEC);
200+
if (ret)
201+
goto err;
202+
203+
val = 0;
204+
snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_TX, i);
205+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
206+
key, &val, ADF_DEC);
207+
if (ret)
208+
goto err;
209+
210+
val = 1;
211+
snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_RX, i);
212+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
213+
key, &val, ADF_DEC);
214+
if (ret)
215+
goto err;
216+
217+
val = ADF_COALESCING_DEF_TIME;
218+
snprintf(key, sizeof(key), ADF_ETRMGR_COALESCE_TIMER_FORMAT, i);
219+
ret = adf_cfg_add_key_value_param(accel_dev, "Accelerator0",
220+
key, &val, ADF_DEC);
221+
if (ret)
222+
goto err;
223+
}
224+
225+
val = i;
226+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC,
227+
&val, ADF_DEC);
228+
if (ret)
229+
goto err;
230+
231+
val = 0;
232+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY,
233+
&val, ADF_DEC);
234+
if (ret)
235+
goto err;
236+
237+
return 0;
238+
err:
239+
dev_err(&GET_DEV(accel_dev), "Failed to add configuration for compression\n");
240+
return ret;
241+
}
242+
243+
int adf_gen4_dev_config(struct adf_accel_dev *accel_dev)
244+
{
245+
char services[ADF_CFG_MAX_VAL_LEN_IN_BYTES] = {0};
246+
int ret;
247+
248+
ret = adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC);
249+
if (ret)
250+
goto err;
251+
252+
ret = adf_cfg_section_add(accel_dev, "Accelerator0");
253+
if (ret)
254+
goto err;
255+
256+
ret = adf_cfg_get_param_value(accel_dev, ADF_GENERAL_SEC,
257+
ADF_SERVICES_ENABLED, services);
258+
if (ret)
259+
goto err;
260+
261+
ret = sysfs_match_string(services_operations, services);
262+
if (ret < 0)
263+
goto err;
264+
265+
switch (ret) {
266+
case DEV_CFG_CY:
267+
ret = adf_crypto_dev_config(accel_dev);
268+
break;
269+
case DEV_CFG_DC:
270+
ret = adf_comp_dev_config(accel_dev);
271+
break;
272+
}
273+
274+
if (ret)
275+
goto err;
276+
277+
set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status);
278+
279+
return ret;
280+
281+
err:
282+
dev_err(&GET_DEV(accel_dev), "Failed to configure QAT driver\n");
168283
return ret;
169284
}
170285

@@ -300,7 +415,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
300415
if (ret)
301416
goto out_err_disable_aer;
302417

303-
ret = adf_crypto_dev_config(accel_dev);
418+
ret = hw_data->dev_config(accel_dev);
304419
if (ret)
305420
goto out_err_disable_aer;
306421

‎drivers/crypto/qat/qat_common/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ intel_qat-objs := adf_cfg.o \
1616
adf_gen4_hw_data.o \
1717
adf_gen4_pm.o \
1818
adf_gen2_dc.o \
19+
adf_gen4_dc.o \
1920
qat_crypto.o \
2021
qat_compression.o \
2122
qat_comp_algs.o \

‎drivers/crypto/qat/qat_common/adf_gen4_dc.c‎

Lines changed: 83 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,83 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
2+
/* Copyright(c) 2022 Intel Corporation */
3+
#include "adf_accel_devices.h"
4+
#include "icp_qat_fw_comp.h"
5+
#include "icp_qat_hw_20_comp.h"
6+
#include "adf_gen4_dc.h"
7+
8+
static void qat_comp_build_deflate(void *ctx)
9+
{
10+
struct icp_qat_fw_comp_req *req_tmpl =
11+
(struct icp_qat_fw_comp_req *)ctx;
12+
struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
13+
struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
14+
struct icp_qat_fw_comp_req_params *req_pars = &req_tmpl->comp_pars;
15+
struct icp_qat_hw_comp_20_config_csr_upper hw_comp_upper_csr = {0};
16+
struct icp_qat_hw_comp_20_config_csr_lower hw_comp_lower_csr = {0};
17+
struct icp_qat_hw_decomp_20_config_csr_lower hw_decomp_lower_csr = {0};
18+
u32 upper_val;
19+
u32 lower_val;
20+
21+
memset(req_tmpl, 0, sizeof(*req_tmpl));
22+
header->hdr_flags =
23+
ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
24+
header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
25+
header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
26+
header->comn_req_flags =
27+
ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_16BYTE_DATA,
28+
QAT_COMN_PTR_TYPE_SGL);
29+
header->serv_specif_flags =
30+
ICP_QAT_FW_COMP_FLAGS_BUILD(ICP_QAT_FW_COMP_STATELESS_SESSION,
31+
ICP_QAT_FW_COMP_AUTO_SELECT_BEST,
32+
ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
33+
ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
34+
ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF);
35+
hw_comp_lower_csr.skip_ctrl = ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL;
36+
hw_comp_lower_csr.algo = ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77;
37+
hw_comp_lower_csr.lllbd = ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED;
38+
hw_comp_lower_csr.sd = ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1;
39+
hw_comp_lower_csr.hash_update = ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW;
40+
hw_comp_lower_csr.edmm = ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED;
41+
hw_comp_upper_csr.nice = ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL;
42+
hw_comp_upper_csr.lazy = ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL;
43+
44+
upper_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(hw_comp_upper_csr);
45+
lower_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(hw_comp_lower_csr);
46+
47+
cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
48+
cd_pars->u.sl.comp_slice_cfg_word[1] = upper_val;
49+
50+
req_pars->crc.legacy.initial_adler = COMP_CPR_INITIAL_ADLER;
51+
req_pars->crc.legacy.initial_crc32 = COMP_CPR_INITIAL_CRC;
52+
req_pars->req_par_flags =
53+
ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(ICP_QAT_FW_COMP_SOP,
54+
ICP_QAT_FW_COMP_EOP,
55+
ICP_QAT_FW_COMP_BFINAL,
56+
ICP_QAT_FW_COMP_CNV,
57+
ICP_QAT_FW_COMP_CNV_RECOVERY,
58+
ICP_QAT_FW_COMP_NO_CNV_DFX,
59+
ICP_QAT_FW_COMP_CRC_MODE_LEGACY,
60+
ICP_QAT_FW_COMP_NO_XXHASH_ACC,
61+
ICP_QAT_FW_COMP_CNV_ERROR_NONE,
62+
ICP_QAT_FW_COMP_NO_APPEND_CRC,
63+
ICP_QAT_FW_COMP_NO_DROP_DATA);
64+
65+
/* Fill second half of the template for decompression */
66+
memcpy(req_tmpl + 1, req_tmpl, sizeof(*req_tmpl));
67+
req_tmpl++;
68+
header = &req_tmpl->comn_hdr;
69+
header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
70+
cd_pars = &req_tmpl->cd_pars;
71+
72+
hw_decomp_lower_csr.algo = ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE;
73+
lower_val = ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(hw_decomp_lower_csr);
74+
75+
cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
76+
cd_pars->u.sl.comp_slice_cfg_word[1] = 0;
77+
}
78+
79+
void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops)
80+
{
81+
dc_ops->build_deflate_ctx = qat_comp_build_deflate;
82+
}
83+
EXPORT_SYMBOL_GPL(adf_gen4_init_dc_ops);

‎drivers/crypto/qat/qat_common/adf_gen4_dc.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
2+
/* Copyright(c) 2022 Intel Corporation */
3+
#ifndef ADF_GEN4_DC_H
4+
#define ADF_GEN4_DC_H
5+
6+
#include "adf_accel_devices.h"
7+
8+
void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops);
9+
10+
#endif /* ADF_GEN4_DC_H */

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