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Merge tag 'timers-clocksource-2025-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull clocksource/event updates from Thomas Gleixner: - Add support for suspend/resume in the STM32 LP-Timer driver with a follow up fix, which uses the proper method to setup the timer as a optional wakeup source instead of trying to force it as mandatory wakeup source. - The usual device tree updates to enable new SoC models in existing drivers. - Trivial spelling, style and indentation fixes * tag 'timers-clocksource-2025-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: dt-bindings: timer: Add SiFive CLINT2 clocksource/drivers/stm32-lptimer: Use wakeup capable instead of init wakeup clocksource/drivers/exynos_mct: Fixed a spelling error clocksource/drivers/stm32-lptimer: Add support for suspend / resume dt-bindings: timer: exynos4210-mct: add samsung,exynos2200-mct-peris compatible dt-bindings: timer: exynos4210-mct: Add samsung,exynos990-mct compatible dt-bindings: timer: Correct indentation and style in DTS example
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‎Documentation/devicetree/bindings/timer/arm,twd-timer.yaml‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ examples:
5050
#include <dt-bindings/interrupt-controller/arm-gic.h>
5151
5252
timer@2c000600 {
53-
compatible = "arm,arm11mp-twd-timer";
54-
reg = <0x2c000600 0x20>;
55-
interrupts = <GIC_PPI 13 0xf01>;
53+
compatible = "arm,arm11mp-twd-timer";
54+
reg = <0x2c000600 0x20>;
55+
interrupts = <GIC_PPI 13 0xf01>;
5656
};

‎Documentation/devicetree/bindings/timer/renesas,cmt.yaml‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -178,29 +178,29 @@ examples:
178178
#include <dt-bindings/interrupt-controller/arm-gic.h>
179179
#include <dt-bindings/power/r8a7790-sysc.h>
180180
cmt0: timer@ffca0000 {
181-
compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
182-
reg = <0xffca0000 0x1004>;
183-
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
184-
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
185-
clocks = <&cpg CPG_MOD 124>;
186-
clock-names = "fck";
187-
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
188-
resets = <&cpg 124>;
181+
compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
182+
reg = <0xffca0000 0x1004>;
183+
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
184+
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
185+
clocks = <&cpg CPG_MOD 124>;
186+
clock-names = "fck";
187+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
188+
resets = <&cpg 124>;
189189
};
190190
191191
cmt1: timer@e6130000 {
192-
compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
193-
reg = <0xe6130000 0x1004>;
194-
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
195-
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
196-
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
197-
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
198-
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
199-
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
200-
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
201-
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
202-
clocks = <&cpg CPG_MOD 329>;
203-
clock-names = "fck";
204-
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
205-
resets = <&cpg 329>;
192+
compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
193+
reg = <0xe6130000 0x1004>;
194+
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
195+
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
196+
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
197+
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
198+
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
199+
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
200+
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
201+
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
202+
clocks = <&cpg CPG_MOD 329>;
203+
clock-names = "fck";
204+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
205+
resets = <&cpg 329>;
206206
};

‎Documentation/devicetree/bindings/timer/renesas,em-sti.yaml‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -38,9 +38,9 @@ examples:
3838
- |
3939
#include <dt-bindings/interrupt-controller/arm-gic.h>
4040
timer@e0180000 {
41-
compatible = "renesas,em-sti";
42-
reg = <0xe0180000 0x54>;
43-
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
44-
clocks = <&sti_sclk>;
45-
clock-names = "sclk";
41+
compatible = "renesas,em-sti";
42+
reg = <0xe0180000 0x54>;
43+
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
44+
clocks = <&sti_sclk>;
45+
clock-names = "sclk";
4646
};

‎Documentation/devicetree/bindings/timer/renesas,mtu2.yaml‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -66,11 +66,11 @@ examples:
6666
#include <dt-bindings/clock/r7s72100-clock.h>
6767
#include <dt-bindings/interrupt-controller/arm-gic.h>
6868
mtu2: timer@fcff0000 {
69-
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
70-
reg = <0xfcff0000 0x400>;
71-
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
72-
interrupt-names = "tgi0a";
73-
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
74-
clock-names = "fck";
75-
power-domains = <&cpg_clocks>;
69+
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
70+
reg = <0xfcff0000 0x400>;
71+
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
72+
interrupt-names = "tgi0a";
73+
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
74+
clock-names = "fck";
75+
power-domains = <&cpg_clocks>;
7676
};

‎Documentation/devicetree/bindings/timer/renesas,ostm.yaml‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -71,9 +71,9 @@ examples:
7171
#include <dt-bindings/clock/r7s72100-clock.h>
7272
#include <dt-bindings/interrupt-controller/arm-gic.h>
7373
ostm0: timer@fcfec000 {
74-
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
75-
reg = <0xfcfec000 0x30>;
76-
interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
77-
clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
78-
power-domains = <&cpg_clocks>;
74+
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
75+
reg = <0xfcfec000 0x30>;
76+
interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
77+
clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
78+
power-domains = <&cpg_clocks>;
7979
};

‎Documentation/devicetree/bindings/timer/renesas,tmu.yaml‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -122,15 +122,15 @@ examples:
122122
#include <dt-bindings/interrupt-controller/arm-gic.h>
123123
#include <dt-bindings/power/r8a7779-sysc.h>
124124
tmu0: timer@ffd80000 {
125-
compatible = "renesas,tmu-r8a7779", "renesas,tmu";
126-
reg = <0xffd80000 0x30>;
127-
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
128-
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
129-
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
130-
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
131-
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
132-
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
133-
clock-names = "fck";
134-
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
135-
#renesas,channels = <3>;
125+
compatible = "renesas,tmu-r8a7779", "renesas,tmu";
126+
reg = <0xffd80000 0x30>;
127+
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
128+
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
129+
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
130+
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
131+
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
132+
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
133+
clock-names = "fck";
134+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
135+
#renesas,channels = <3>;
136136
};

‎Documentation/devicetree/bindings/timer/renesas,tpu.yaml‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -49,8 +49,8 @@ additionalProperties: false
4949
examples:
5050
- |
5151
tpu: tpu@ffffe0 {
52-
compatible = "renesas,tpu";
53-
reg = <0xffffe0 16>, <0xfffff0 12>;
54-
clocks = <&pclk>;
55-
clock-names = "fck";
52+
compatible = "renesas,tpu";
53+
reg = <0xffffe0 16>, <0xfffff0 12>;
54+
clocks = <&pclk>;
55+
clock-names = "fck";
5656
};

‎Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,13 +27,15 @@ properties:
2727
- enum:
2828
- axis,artpec8-mct
2929
- google,gs101-mct
30+
- samsung,exynos2200-mct-peris
3031
- samsung,exynos3250-mct
3132
- samsung,exynos5250-mct
3233
- samsung,exynos5260-mct
3334
- samsung,exynos5420-mct
3435
- samsung,exynos5433-mct
3536
- samsung,exynos850-mct
3637
- samsung,exynos8895-mct
38+
- samsung,exynos990-mct
3739
- tesla,fsd-mct
3840
- const: samsung,exynos4210-mct
3941

@@ -130,11 +132,13 @@ allOf:
130132
enum:
131133
- axis,artpec8-mct
132134
- google,gs101-mct
135+
- samsung,exynos2200-mct-peris
133136
- samsung,exynos5260-mct
134137
- samsung,exynos5420-mct
135138
- samsung,exynos5433-mct
136139
- samsung,exynos850-mct
137140
- samsung,exynos8895-mct
141+
- samsung,exynos990-mct
138142
then:
139143
properties:
140144
interrupts:

‎Documentation/devicetree/bindings/timer/sifive,clint.yaml‎

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,12 @@ properties:
3636
- starfive,jh7110-clint # StarFive JH7110
3737
- starfive,jh8100-clint # StarFive JH8100
3838
- const: sifive,clint0 # SiFive CLINT v0 IP block
39+
- items:
40+
- {}
41+
- const: sifive,clint2 # SiFive CLINT v2 IP block
42+
description:
43+
SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
44+
differs from that of sifive,clint0, making them incompatible.
3945
- items:
4046
- enum:
4147
- allwinner,sun20i-d1-clint
@@ -62,6 +68,22 @@ properties:
6268
minItems: 1
6369
maxItems: 4095
6470

71+
sifive,fine-ctr-bits:
72+
maximum: 15
73+
description: The width in bits of the fine counter.
74+
75+
if:
76+
properties:
77+
compatible:
78+
contains:
79+
const: sifive,clint2
80+
then:
81+
required:
82+
- sifive,fine-ctr-bits
83+
else:
84+
properties:
85+
sifive,fine-ctr-bits: false
86+
6587
additionalProperties: false
6688

6789
required:
@@ -77,6 +99,6 @@ examples:
7799
<&cpu2intc 3>, <&cpu2intc 7>,
78100
<&cpu3intc 3>, <&cpu3intc 7>,
79101
<&cpu4intc 3>, <&cpu4intc 7>;
80-
reg = <0x2000000 0x10000>;
102+
reg = <0x2000000 0x10000>;
81103
};
82104
...

‎drivers/clocksource/exynos_mct.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -238,7 +238,7 @@ static cycles_t exynos4_read_current_timer(void)
238238
static int __init exynos4_clocksource_init(bool frc_shared)
239239
{
240240
/*
241-
* When the frc is shared, the main processer should have already
241+
* When the frc is shared, the main processor should have already
242242
* turned it on and we shouldn't be writing to TCON.
243243
*/
244244
if (frc_shared)

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