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Merge pull request ARMmbed#14699 from jeromecoutant/PR_ASTYLE
STM32 astyle format
2 parents 8a0c3c7 + c69654f commit da13755

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41 files changed

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‎connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c‎

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -61,14 +61,13 @@
6161
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
6262
{
6363
GPIO_InitTypeDef GPIO_InitStruct;
64-
if(heth->Instance == ETH)
65-
{
64+
if (heth->Instance == ETH) {
6665
enableEthPowerSupply();
67-
68-
#if !(defined(DUAL_CORE) && defined(CORE_CM4))
66+
67+
#if !(defined(DUAL_CORE) && defined(CORE_CM4))
6968
/* Disable DCache for STM32H7 family */
7069
SCB_DisableDCache();
71-
#endif
70+
#endif
7271

7372
/* GPIO Ports Clock Enable */
7473
__HAL_RCC_GPIOA_CLK_ENABLE();
@@ -118,21 +117,21 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
118117
PC4 ------> ETH_RXD0
119118
PC5 ------> ETH_RXD1
120119
*/
121-
GPIO_InitStruct.Pin = ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin;
120+
GPIO_InitStruct.Pin = ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin;
122121
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
123122
GPIO_InitStruct.Pull = GPIO_NOPULL;
124123
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
125124
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
126125
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
127126

128-
GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin;
127+
GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin;
129128
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
130129
GPIO_InitStruct.Pull = GPIO_NOPULL;
131130
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
132131
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
133132
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
134133

135-
GPIO_InitStruct.Pin = ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin;
134+
GPIO_InitStruct.Pin = ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin;
136135
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
137136
GPIO_InitStruct.Pull = GPIO_NOPULL;
138137
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
@@ -146,8 +145,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
146145
*/
147146
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
148147
{
149-
if(heth->Instance == ETH)
150-
{
148+
if (heth->Instance == ETH) {
151149
/* Peripheral clock disable */
152150
__HAL_RCC_ETH1MAC_CLK_DISABLE();
153151
__HAL_RCC_ETH1TX_CLK_DISABLE();
@@ -164,11 +162,11 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
164162
PC4 ------> ETH_RXD0
165163
PC5 ------> ETH_RXD1
166164
*/
167-
HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin);
165+
HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin);
168166

169-
HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin);
167+
HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin);
170168

171-
HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin);
169+
HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin);
172170

173171
HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0);
174172
}

‎targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F070xB/system_clock.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
9595
//Select HSI as system clock source to allow modification of the PLL configuration
9696
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
9797
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
98-
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
98+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
9999
return 0; // FAIL
100100
}
101101

‎targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F072xB/system_clock.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
9595
//Select HSI as system clock source to allow modification of the PLL configuration
9696
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
9797
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
98-
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
98+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
9999
return 0; // FAIL
100100
}
101101

‎targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F091xC/system_clock.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
9595
//Select HSI as system clock source to allow modification of the PLL configuration
9696
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
9797
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
98-
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
98+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
9999
return 0; // FAIL
100100
}
101101

‎targets/TARGET_STM/TARGET_STM32F0/cmsis_nvic.c‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -18,24 +18,26 @@
1818

1919
#define NVIC_USER_IRQ_OFFSET 16
2020

21-
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
21+
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
22+
{
2223
int i;
2324

2425
// Copy and switch to dynamic vectors if first time called
2526
if ((SYSCFG->CFGR1 & SYSCFG_CFGR1_MEM_MODE) != SYSCFG_CFGR1_MEM_MODE) {
2627
uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
2728
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
28-
*((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (i*4))) = old_vectors[i];
29+
*((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (i * 4))) = old_vectors[i];
2930
}
3031
SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE; // Embedded SRAM mapped at 0x00000000
3132
}
3233

3334
// Set the vector
34-
*((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (IRQn*4) + (NVIC_USER_IRQ_OFFSET*4))) = vector;
35+
*((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (IRQn * 4) + (NVIC_USER_IRQ_OFFSET * 4))) = vector;
3536
}
3637

37-
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
38-
uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
38+
uint32_t NVIC_GetVector(IRQn_Type IRQn)
39+
{
40+
uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
3941
// Return the vector
4042
return vectors[IRQn + 16];
4143
}

‎targets/TARGET_STM/TARGET_STM32F0/us_ticker_data.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
#define __US_TICKER_DATA_H
1818

1919
#ifdef __cplusplus
20-
extern "C" {
20+
extern "C" {
2121
#endif
2222

2323
#include "stm32f0xx.h"

‎targets/TARGET_STM/TARGET_STM32F3/us_ticker_data.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,13 +18,13 @@
1818
#define __US_TICKER_DATA_H
1919

2020
#ifdef __cplusplus
21-
extern "C" {
21+
extern "C" {
2222
#endif
2323

2424
#include "stm32f3xx.h"
2525
#include "stm32f3xx_ll_tim.h"
2626
#include "cmsis_nvic.h"
27-
27+
2828
#define TIM_MST TIM2
2929
#define TIM_MST_IRQ TIM2_IRQn
3030
#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE()

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -106,8 +106,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
106106
HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
107107

108108
/* PLL could be already configured by bootlader */
109-
if (RCC_OscInitStruct.PLL.PLLState != RCC_PLL_ON)
110-
{
109+
if (RCC_OscInitStruct.PLL.PLLState != RCC_PLL_ON) {
111110
/* Enable HSE oscillator and activate PLL with HSE as source */
112111
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
113112
if (bypass == 0) {

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/TargetInit.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,8 @@
1515

1616
#include "stm32f4xx.h"
1717

18-
void TargetBSP_Init(void) {
18+
void TargetBSP_Init(void)
19+
{
1920
/* In DISCO_F413ZH board, Arduino connector and Wifi embeded module are sharing the same SPI pins */
2021
/* We need to set the default SPI SS pin for the Wifi module to the inactive state i.e. 1 */
2122
/* See board User Manual: WIFI_SPI_CS = PG_11*/

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -290,7 +290,7 @@ typedef enum {
290290
D69 = PF_1,
291291
D70 = PF_2,
292292
D71 = PA_7,
293-
293+
294294
// STDIO for console print
295295
#ifdef MBED_CONF_TARGET_STDIO_UART_TX
296296
CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX,
@@ -394,4 +394,3 @@ typedef enum {
394394
#endif
395395

396396
#endif
397-

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