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jeromecoutantjeromecoutant
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STM32H7 astyle
1 parent 9cadad3 commit cfd8688

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3 files changed

+67
-66
lines changed

3 files changed

+67
-66
lines changed

‎connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c‎

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -61,14 +61,13 @@
6161
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
6262
{
6363
GPIO_InitTypeDef GPIO_InitStruct;
64-
if(heth->Instance == ETH)
65-
{
64+
if (heth->Instance == ETH) {
6665
enableEthPowerSupply();
67-
68-
#if !(defined(DUAL_CORE) && defined(CORE_CM4))
66+
67+
#if !(defined(DUAL_CORE) && defined(CORE_CM4))
6968
/* Disable DCache for STM32H7 family */
7069
SCB_DisableDCache();
71-
#endif
70+
#endif
7271

7372
/* GPIO Ports Clock Enable */
7473
__HAL_RCC_GPIOA_CLK_ENABLE();
@@ -118,21 +117,21 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
118117
PC4 ------> ETH_RXD0
119118
PC5 ------> ETH_RXD1
120119
*/
121-
GPIO_InitStruct.Pin = ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin;
120+
GPIO_InitStruct.Pin = ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin;
122121
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
123122
GPIO_InitStruct.Pull = GPIO_NOPULL;
124123
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
125124
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
126125
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
127126

128-
GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin;
127+
GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin;
129128
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
130129
GPIO_InitStruct.Pull = GPIO_NOPULL;
131130
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
132131
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
133132
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
134133

135-
GPIO_InitStruct.Pin = ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin;
134+
GPIO_InitStruct.Pin = ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin;
136135
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
137136
GPIO_InitStruct.Pull = GPIO_NOPULL;
138137
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
@@ -146,8 +145,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
146145
*/
147146
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
148147
{
149-
if(heth->Instance == ETH)
150-
{
148+
if (heth->Instance == ETH) {
151149
/* Peripheral clock disable */
152150
__HAL_RCC_ETH1MAC_CLK_DISABLE();
153151
__HAL_RCC_ETH1TX_CLK_DISABLE();
@@ -164,11 +162,11 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
164162
PC4 ------> ETH_RXD0
165163
PC5 ------> ETH_RXD1
166164
*/
167-
HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin);
165+
HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin);
168166

169-
HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin);
167+
HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin);
170168

171-
HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin);
169+
HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin);
172170

173171
HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0);
174172
}

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -26,27 +26,27 @@
2626
******************************************************************************/
2727
void enableEthPowerSupply(void)
2828
{
29-
/* Ensure ETH power supply */
30-
mbed::I2C i2c(PB_7, PB_6);
31-
32-
char data[2];
33-
34-
// LDO3 to 1.2V
35-
data[0]=0x52;
36-
data[1]=0x9;
37-
i2c.write(8 << 1, data, sizeof(data));
38-
data[0]=0x53;
39-
data[1]=0xF;
40-
i2c.write(8 << 1, data, sizeof(data));
41-
42-
// SW2 to 3.3V (SW2_VOLT)
43-
data[0]=0x3B;
44-
data[1]=0xF;
45-
i2c.write(8 << 1, data, sizeof(data));
46-
47-
// SW1 to 3.0V (SW1_VOLT)
48-
data[0]=0x35;
49-
data[1]=0xF;
50-
i2c.write(8 << 1, data, sizeof(data));
51-
29+
/* Ensure ETH power supply */
30+
mbed::I2C i2c(PB_7, PB_6);
31+
32+
char data[2];
33+
34+
// LDO3 to 1.2V
35+
data[0] = 0x52;
36+
data[1] = 0x9;
37+
i2c.write(8 << 1, data, sizeof(data));
38+
data[0] = 0x53;
39+
data[1] = 0xF;
40+
i2c.write(8 << 1, data, sizeof(data));
41+
42+
// SW2 to 3.3V (SW2_VOLT)
43+
data[0] = 0x3B;
44+
data[1] = 0xF;
45+
i2c.write(8 << 1, data, sizeof(data));
46+
47+
// SW1 to 3.0V (SW1_VOLT)
48+
data[0] = 0x35;
49+
data[1] = 0xF;
50+
i2c.write(8 << 1, data, sizeof(data));
51+
5252
}

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c‎

Lines changed: 33 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -68,9 +68,9 @@ uint8_t SetSysClock_PLL_HSI(void);
6868
void SetSysClock(void)
6969
{
7070

71-
bool lowspeed = false;
71+
bool lowspeed = false;
7272
#if defined(LOWSPEED) && (LOWSPEED == 1)
73-
lowspeed = true;
73+
lowspeed = true;
7474
#endif
7575

7676
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
@@ -95,17 +95,19 @@ void SetSysClock(void)
9595
}
9696

9797
static const uint32_t _keep;
98-
bool isBootloader() {
99-
return ((uint32_t)&_keep < 0x8040000);
98+
bool isBootloader()
99+
{
100+
return ((uint32_t)&_keep < 0x8040000);
100101
}
101102

102-
bool isBetaBoard() {
103-
uint8_t* bootloader_data = (uint8_t*)(0x801F000);
104-
if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) {
105-
return true;
106-
} else {
107-
return (bootloader_data[10] == 27);
108-
}
103+
bool isBetaBoard()
104+
{
105+
uint8_t *bootloader_data = (uint8_t *)(0x801F000);
106+
if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) {
107+
return true;
108+
} else {
109+
return (bootloader_data[10] == 27);
110+
}
109111
}
110112

111113
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
@@ -118,14 +120,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
118120
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
119121
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
120122

121-
// If we are reconfiguring the clock, select CSI as system clock source to allow modification of the PLL configuration
123+
// If we are reconfiguring the clock, select CSI as system clock source to allow modification of the PLL configuration
122124
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) {
123-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
124-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI;
125-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
126-
{
127-
return 0;
128-
}
125+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
126+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI;
127+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
128+
return 0;
129+
}
129130
}
130131

131132
/* Enable oscillator pin */
@@ -148,9 +149,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
148149
/* Configure the main internal regulator output voltage */
149150

150151
if (lowspeed) {
151-
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
152+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
152153
} else {
153-
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
154+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
154155
}
155156

156157
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
@@ -167,17 +168,17 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
167168
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
168169
RCC_OscInitStruct.PLL.PLLM = 5;
169170
if (lowspeed) {
170-
RCC_OscInitStruct.PLL.PLLN = 40;
171+
RCC_OscInitStruct.PLL.PLLN = 40;
171172
} else {
172-
RCC_OscInitStruct.PLL.PLLN = 160;
173+
RCC_OscInitStruct.PLL.PLLN = 160;
173174
}
174175

175176
#if HSE_VALUE == 27000000
176177
RCC_OscInitStruct.PLL.PLLM = 9;
177178
if (lowspeed) {
178-
RCC_OscInitStruct.PLL.PLLN = 80;
179+
RCC_OscInitStruct.PLL.PLLN = 80;
179180
} else {
180-
RCC_OscInitStruct.PLL.PLLN = 300;
181+
RCC_OscInitStruct.PLL.PLLN = 300;
181182
}
182183
#endif
183184

@@ -203,11 +204,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
203204
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
204205
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
205206
if (lowspeed) {
206-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
207-
return 0; // FAIL
207+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
208+
return 0; // FAIL
209+
}
208210
} else {
209-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
210-
return 0; // FAIL
211+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
212+
return 0; // FAIL
213+
}
211214
}
212215

213216
// HAL_RCCEx_EnableBootCore(RCC_BOOT_C2);
@@ -294,13 +297,13 @@ uint8_t SetSysClock_PLL_HSI(void)
294297
#if defined (CORE_CM4)
295298
void HSEM2_IRQHandler(void)
296299
{
297-
HAL_HSEM_IRQHandler();
300+
HAL_HSEM_IRQHandler();
298301
}
299302
#endif
300303

301304
#if defined (CORE_CM7)
302305
void HSEM1_IRQHandler(void)
303306
{
304-
HAL_HSEM_IRQHandler();
307+
HAL_HSEM_IRQHandler();
305308
}
306309
#endif

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