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Merge pull request ARMmbed#14623 from s-bruce13/master
Updated SDK 2.9.1 and added Flash Support for MIMXRT1170_EVK
2 parents d64d0b7 + 659f0bb commit 640d844

36 files changed

+37475
-24828
lines changed

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/CMakeLists.txt‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,6 @@ target_sources(mbed-mimxrt1170-evk
2626
device/system_MIMXRT1176_cm7.c
2727

2828
drivers/fsl_anatop_ai.c
29-
drivers/fsl_anatop.c
3029
drivers/fsl_cache.c
3130
drivers/fsl_clock.c
3231
drivers/fsl_common.c

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.c‎

Lines changed: 728 additions & 72 deletions
Large diffs are not rendered by default.

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.h‎

Lines changed: 145 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2018-2019 NXP
2+
* Copyright 2020 NXP
33
* All rights reserved.
44
*
55
* SPDX-License-Identifier: BSD-3-Clause
@@ -13,29 +13,11 @@
1313
/*******************************************************************************
1414
* Definitions
1515
******************************************************************************/
16-
#if (defined(CPU_MIMXRT1171AVM8A) || \
17-
defined(CPU_MIMXRT1172AVM8A) || \
18-
defined(CPU_MIMXRT1175AVM8A_cm7) || defined(CPU_MIMXRT1175AVM8A_cm4) || \
19-
defined(CPU_MIMXRT1176AVM8A_cm7) || defined(CPU_MIMXRT1176AVM8A_cm4))
20-
#define AUTOMOTIVE_SERIES
21-
#elif (defined(CPU_MIMXRT1171CVM8A) || \
22-
defined(CPU_MIMXRT1172CVM8A) || \
23-
defined(CPU_MIMXRT1173CVM8A_cm7) || defined(CPU_MIMXRT1173CVM8A_cm4) || \
24-
defined(CPU_MIMXRT1175CVM8A_cm7) || defined(CPU_MIMXRT1175CVM8A_cm4) || \
25-
defined(CPU_MIMXRT1176CVM8A_cm7) || defined(CPU_MIMXRT1176CVM8A_cm4))
26-
#define INDUSTRIAL_SERIES
27-
#elif (defined(CPU_MIMXRT1171DVMAA) || \
28-
defined(CPU_MIMXRT1172DVMAA) || \
29-
defined(CPU_MIMXRT1175DVMAA_cm7) || defined(CPU_MIMXRT1175DVMAA_cm4) || \
30-
defined(CPU_MIMXRT1176DVMAA_cm7) || defined(CPU_MIMXRT1176DVMAA_cm4))
31-
#define CONSUMER_SERIES
32-
#else
33-
#error "No valid CPU defined!"
34-
#endif
3516

3617
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
3718

38-
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
19+
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
20+
3921
/*******************************************************************************
4022
************************ BOARD_InitBootClocks function ************************
4123
******************************************************************************/
@@ -60,57 +42,148 @@ void BOARD_InitBootClocks(void);
6042
/*******************************************************************************
6143
* Definitions for BOARD_BootClockRUN configuration
6244
******************************************************************************/
63-
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
45+
#if __CORTEX_M == 7
46+
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */
47+
#else
48+
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 392727272UL /*!< CM4 Core clock frequency: 392727272Hz */
49+
#endif
6450

6551
/* Clock outputs (values are in Hz): */
66-
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
67-
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
68-
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
69-
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
70-
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
71-
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
72-
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
73-
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
74-
#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
75-
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
76-
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL
77-
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
78-
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
79-
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
80-
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
81-
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
82-
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
83-
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
84-
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
85-
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
86-
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL
87-
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
88-
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
89-
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
90-
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
91-
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
92-
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
93-
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
94-
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
95-
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
96-
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
97-
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
98-
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
99-
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
100-
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
101-
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
102-
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
103-
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
104-
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
105-
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
106-
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
107-
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
108-
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
109-
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
110-
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
111-
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
112-
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
113-
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
52+
#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL
53+
#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL
54+
#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL
55+
#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL
56+
#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL
57+
#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL
58+
#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL
59+
#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL
60+
#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL
61+
#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL
62+
#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL
63+
#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL
64+
#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL
65+
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
66+
#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL
67+
#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL
68+
#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL
69+
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL
70+
#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL
71+
#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 24000000UL
72+
#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL
73+
#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL
74+
#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL
75+
#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL
76+
#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL
77+
#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL
78+
#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL
79+
#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL
80+
#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL
81+
#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL
82+
#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL
83+
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 24000000UL
84+
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL
85+
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL
86+
#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL
87+
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL
88+
#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL
89+
#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL
90+
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL
91+
#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL
92+
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL
93+
#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL
94+
#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL
95+
#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL
96+
#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL
97+
#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL
98+
#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL
99+
#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL
100+
#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL
101+
#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL
102+
#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL
103+
#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL
104+
#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL
105+
#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL
106+
#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL
107+
#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL
108+
#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL
109+
#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL
110+
#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL
111+
#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL
112+
#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL
113+
#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL
114+
#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL
115+
#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL
116+
#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL
117+
#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL
118+
#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL
119+
#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL
120+
#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL
121+
#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL
122+
#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL
123+
#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL
124+
#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL
125+
#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL
126+
#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 392727272UL
127+
#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL
128+
#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL
129+
#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL
130+
#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL
131+
#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL
132+
#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL
133+
#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL
134+
#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL
135+
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL
136+
#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL
137+
#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL
138+
#define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL
139+
#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL
140+
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL
141+
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL
142+
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL
143+
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL
144+
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL
145+
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL
146+
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL
147+
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL
148+
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL
149+
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL
150+
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL
151+
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL
152+
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL
153+
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL
154+
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
155+
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL
156+
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL
157+
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL
158+
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
159+
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL
160+
#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL
161+
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL
162+
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL
163+
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL
164+
#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL
165+
#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL
166+
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL
167+
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL
168+
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL
169+
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL
170+
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL
171+
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL
172+
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL
173+
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL
174+
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL
175+
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL
176+
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL
177+
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL
178+
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL
179+
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL
180+
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL
181+
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL
182+
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL
183+
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL
184+
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL
185+
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL
186+
114187

115188
/*******************************************************************************
116189
* API for BOARD_BootClockRUN configuration
@@ -129,4 +202,5 @@ void BOARD_BootClockRUN(void);
129202
}
130203
#endif /* __cplusplus*/
131204

132-
#endif /* _FSL_CLOCK_CONFIG_H_ */
205+
#endif /* _CLOCK_CONFIG_H_ */
206+

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/device.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -23,10 +23,10 @@
2323

2424

2525

26-
#define BOARD_FLASH_SIZE (0x800000U)
27-
#define BOARD_FLASH_START_ADDR (0x60000000U)
28-
#define BOARD_FLASHIAP_SIZE (0x7F0000U)
29-
#define BOARD_FLASHIAP_START_ADDR (0x60010000U)
26+
#define BOARD_FLASH_SIZE (0x1000000U)
27+
#define BOARD_FLASH_START_ADDR (0x30000000U)
28+
#define BOARD_FLASHIAP_SIZE (0xFF0000U)
29+
#define BOARD_FLASHIAP_START_ADDR (0x30010000U)
3030
#define BOARD_FLASH_PAGE_SIZE (256)
3131
#define BOARD_FLASH_SECTOR_SIZE (4096)
3232

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