More accurate approximation for multiplication factor of PLL to make 48Mhz.

cmaglie · cmaglie · commit af0263a60a6b · 2017-09-01T21:35:15.000+02:00
Fix #223
diff --git a/CHANGELOG b/CHANGELOG
@@ -1,3 +1,7 @@
+SAMD CORE 1.6.17
+
+* More accurate approximation for multiplication factor of PLL to make 48Mhz. Thanks @joverbee
+
 SAMD CORE 1.6.16 2017.08.23
 
 * Is now possible to use PWM on D7 (though it can't be used with PWM on D12 at the same time). Thanks @Adminius
diff --git a/cores/arduino/startup.c b/cores/arduino/startup.c
@@ -148,7 +148,7 @@ void SystemInit( void )
 
   SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 31 ) | // Coarse step is 31, half of the max value
                          SYSCTRL_DFLLMUL_FSTEP( 511 ) | // Fine step is 511, half of the max value
-                         SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK/VARIANT_MAINOSC) ) ; // External 32KHz is the reference
+                         SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK + VARIANT_MAINOSC/2) / VARIANT_MAINOSC ) ; // External 32KHz is the reference
 
   while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
   {

Original file line number	Diff line number	Diff line change
`@@ -148,7 +148,7 @@ void SystemInit( void )`
`148`	`148`
`149`	`149`	`SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 31 ) \| // Coarse step is 31, half of the max value`
`150`	`150`	`SYSCTRL_DFLLMUL_FSTEP( 511 ) \| // Fine step is 511, half of the max value`
`151`		`- SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK/VARIANT_MAINOSC) ) ; // External 32KHz is the reference`
	`151`	`+ SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK + VARIANT_MAINOSC/2) / VARIANT_MAINOSC ) ; // External 32KHz is the reference`
`152`	`152`
`153`	`153`	`while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )`
`154`	`154`	`{`