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lines changed Original file line number Diff line number Diff line change @@ -240,7 +240,12 @@ void initVariant( void )
240240 variantGpioInit ();
241241 variantPwmInit ();
242242 variantAdcInit ();
243-
243+
244+ // set RTC clock divider to 32768(1 Hz)
245+ *SYS_CLK_CTL |= RTC_DIV_1HZ_MASK;
246+ *SYS_CLK_CTL &= ~(1 << CCU_RTC_CLK_DIV_EN);
247+ *SYS_CLK_CTL |= 1 << CCU_RTC_CLK_DIV_EN;
248+
244249 cfw_platform_init ();
245250
246251 // Add for debug corelib
Original file line number Diff line number Diff line change @@ -146,6 +146,14 @@ extern "C"{
146146#define ADC_RESOLUTION 12
147147#define ADC_CLOCK_GATE (1 << 31)
148148
149+ /*
150+ * Clocking
151+ */
152+
153+ #define SYS_CLK_CTL (volatile int*)0xB0800038
154+ #define CCU_RTC_CLK_DIV_EN 2
155+ #define RTC_DIV_1HZ_MASK 0x00000078
156+
149157#define digitalPinToBitMask (P ) (1 << g_APinDescription[P].ulGPIOId)
150158
151159//static uint8_t __unused_var_POR;
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