add support for Power Management library

Author: bigdinotech

system/libarc32_arduino101/drivers/soc_gpio.c

@@ -34,6 +34,7 @@
 
 #include "soc_register.h"
 #include "portable.h"
+#include "platform.h"
 
 #define GPIO_CLKENA_POS         (31)
 #define GPIO_LS_SYNC_POS        (0)
@@ -429,6 +430,8 @@ static void soc_gpio_ISR_proc( uint32_t dev_id )
     uint32_t status = MMIO_REG_VAL_FROM_BASE(dev->reg_base, SOC_GPIO_INTSTATUS);
     // Mask the pending interrupts
     MMIO_REG_VAL_FROM_BASE(dev->reg_base, SOC_GPIO_INTMASK) |= status;
+    // Save a copy of the INTSTATUS register
+    shared_data->pm_int_status = status;
     // Clear interrupt flag (write 1 to clear)
     MMIO_REG_VAL_FROM_BASE(dev->reg_base, SOC_GPIO_PORTA_EOI) = status;
 

system/libarc32_arduino101/drivers/soc_gpio.h

@@ -43,6 +43,7 @@
 
 #include "data_type.h"
 #include "gpio.h"
+#include "platform.h"
 
 // soc gpio 32 bit count
 #if defined(CONFIG_SOC_GPIO_32)

system/libarc32_arduino101/drivers/ss_gpio_iface.c

@@ -37,6 +37,7 @@
 #include "io_config.h"
 #include "eiaextensions.h"
 #include "portable.h"
+#include "platform.h"
 
 /* EIA GPIO device registers  */
 #define     SWPORTA_DR      (0x00)  /* GPIO Port A Data Register*/
@@ -355,6 +356,8 @@ static void ss_gpio_ISR_proc( uint32_t dev_id )
     uint32_t status = REG_READ( INTSTATUS );
     /* Mask the pending IRQ in order to avoid a storm of interrupts */
     REG_WRITE(INTMASK, REG_READ(INTMASK) | status);
+    // Save a copy of the INTSTATUS register
+    shared_data->pm_int_status = status;
     // Clear interrupt flag (write 1 to clear)
     REG_WRITE( PORTA_EOI, status );
 

system/libarc32_arduino101/drivers/ss_gpio_iface.h

@@ -41,6 +41,7 @@
 
 #include "data_type.h"
 #include "gpio.h"
+#include "platform.h"
 
 #define SS_GPIO_8B0_BITS    (8)
 #define SS_GPIO_8B1_BITS    (8)

system/libarc32_arduino101/framework/include/platform.h

@@ -146,6 +146,16 @@ struct platform_shared_block_ {
 
     struct shared_ring_buffer quark_to_ARC;
     struct shared_ring_buffer ARC_to_quark;
+    
+    uint32_t arc_cpu_context[33];
+    
+    uint32_t pm_status;
+    
+    void* arc_restore_addr;
+    
+    void* quark_restore_addr;
+    
+    uint32_t pm_int_status;
 };
 
 #define RAM_START           0xA8000000