2525
2626UARTClass::UARTClass ( Uart *pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer *pRx_buffer, RingBuffer *pTx_buffer )
2727{
28- _rx_buffer = pRx_buffer ;
28+ _rx_buffer = pRx_buffer;
2929 _tx_buffer = pTx_buffer;
3030
31- _pUart=pUart ;
32- _dwIrq=dwIrq ;
33- _dwId=dwId ;
31+ _pUart=pUart;
32+ _dwIrq=dwIrq;
33+ _dwId=dwId;
3434}
3535
3636// Public Methods //////////////////////////////////////////////////////////////
3737
38-
39-
4038void UARTClass::begin ( const uint32_t dwBaudRate )
4139{
42- begin ( dwBaudRate, UART_MR_PAR_NO | UART_MR_CHMODE_NORMAL );
40+ begin ( dwBaudRate, UART_MR_PAR_NO | UART_MR_CHMODE_NORMAL );
4341}
4442
4543void UARTClass::begin ( const uint32_t dwBaudRate, const uint32_t config )
4644{
4745 // Configure PMC
48- pmc_enable_periph_clk ( _dwId ) ;
46+ pmc_enable_periph_clk ( _dwId );
4947
5048 // Disable PDC channel
51- _pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS ;
49+ _pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS;
5250
5351 // Reset and disable receiver and transmitter
54- _pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS ;
52+ _pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS;
5553
5654 // Configure mode
57- _pUart->UART_MR = config ;
55+ _pUart->UART_MR = config;
5856
5957 // Configure baudrate (asynchronous, no oversampling)
60- _pUart->UART_BRGR = (SystemCoreClock / dwBaudRate) >> 4 ;
58+ _pUart->UART_BRGR = (SystemCoreClock / dwBaudRate) >> 4 ;
6159
6260 // Configure interrupts
6361 _pUart->UART_IDR = 0xFFFFFFFF ;
@@ -66,41 +64,41 @@ void UARTClass::begin( const uint32_t dwBaudRate, const uint32_t config )
6664 // Enable UART interrupt in NVIC
6765 NVIC_EnableIRQ (_dwIrq);
6866
69- // make sure both ring buffers are initialized back to empty.
67+ // Make sure both ring buffers are initialized back to empty.
7068 _rx_buffer->_iHead = _rx_buffer->_iTail = 0 ;
7169 _tx_buffer->_iHead = _tx_buffer->_iTail = 0 ;
7270
7371 // Enable receiver and transmitter
74- _pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN ;
72+ _pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN;
7573}
7674
7775void UARTClass::end ( void )
7876{
79- // clear any received data
80- _rx_buffer->_iHead = _rx_buffer->_iTail ;
77+ // Clear any received data
78+ _rx_buffer->_iHead = _rx_buffer->_iTail ;
8179
8280 // Wait for any outstanding data to be sent
8381 flush ();
8482
8583 // Disable UART interrupt in NVIC
86- NVIC_DisableIRQ ( _dwIrq ) ;
84+ NVIC_DisableIRQ ( _dwIrq );
8785
88- pmc_disable_periph_clk ( _dwId ) ;
86+ pmc_disable_periph_clk ( _dwId );
8987}
9088
9189void UARTClass::setInterruptPriority (uint32_t priority)
9290{
93- NVIC_SetPriority (_dwIrq, priority & 0x0F );
91+ NVIC_SetPriority (_dwIrq, priority & 0x0F );
9492}
9593
9694uint32_t UARTClass::getInterruptPriority ()
9795{
98- return NVIC_GetPriority (_dwIrq);
96+ return NVIC_GetPriority (_dwIrq);
9997}
10098
10199int UARTClass::available ( void )
102100{
103- return (uint32_t )(SERIAL_BUFFER_SIZE + _rx_buffer->_iHead - _rx_buffer->_iTail ) % SERIAL_BUFFER_SIZE ;
101+ return (uint32_t )(SERIAL_BUFFER_SIZE + _rx_buffer->_iHead - _rx_buffer->_iTail ) % SERIAL_BUFFER_SIZE;
104102}
105103
106104int UARTClass::availableForWrite (void )
@@ -114,46 +112,50 @@ int UARTClass::availableForWrite(void)
114112int UARTClass::peek ( void )
115113{
116114 if ( _rx_buffer->_iHead == _rx_buffer->_iTail )
117- return -1 ;
115+ return -1 ;
118116
119- return _rx_buffer->_aucBuffer [_rx_buffer->_iTail ] ;
117+ return _rx_buffer->_aucBuffer [_rx_buffer->_iTail ];
120118}
121119
122120int UARTClass::read ( void )
123121{
124122 // if the head isn't ahead of the tail, we don't have any characters
125123 if ( _rx_buffer->_iHead == _rx_buffer->_iTail )
126- return -1 ;
124+ return -1 ;
127125
128- uint8_t uc = _rx_buffer->_aucBuffer [_rx_buffer->_iTail ] ;
129- _rx_buffer->_iTail = (unsigned int )(_rx_buffer->_iTail + 1 ) % SERIAL_BUFFER_SIZE ;
130- return uc ;
126+ uint8_t uc = _rx_buffer->_aucBuffer [_rx_buffer->_iTail ];
127+ _rx_buffer->_iTail = (unsigned int )(_rx_buffer->_iTail + 1 ) % SERIAL_BUFFER_SIZE;
128+ return uc;
131129}
132130
133131void UARTClass::flush ( void )
134132{
135133 while (_tx_buffer->_iHead != _tx_buffer->_iTail ); // wait for transmit data to be sent
136134 // Wait for transmission to complete
137135 while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY)
138- ;
136+ ;
139137}
140138
141139size_t UARTClass::write ( const uint8_t uc_data )
142140{
143- if (((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY) | (_tx_buffer->_iTail != _tx_buffer->_iHead )) // is the hardware currently busy?
141+ // Is the hardware currently busy?
142+ if (((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY) |
143+ (_tx_buffer->_iTail != _tx_buffer->_iHead ))
144144 {
145- // if busy we buffer
146- unsigned int l = (_tx_buffer->_iHead + 1 ) % SERIAL_BUFFER_SIZE;
147- while (_tx_buffer->_iTail == l); // spin locks if we're about to overwrite the buffer. This continues once the data is sent
148-
149- _tx_buffer->_aucBuffer [_tx_buffer->_iHead ] = uc_data;
150- _tx_buffer->_iHead = l;
151- _pUart->UART_IER = UART_IER_TXRDY; // make sure TX interrupt is enabled
145+ // If busy we buffer
146+ unsigned int l = (_tx_buffer->_iHead + 1 ) % SERIAL_BUFFER_SIZE;
147+ while (_tx_buffer->_iTail == l)
148+ ; // Spin locks if we're about to overwrite the buffer. This continues once the data is sent
149+
150+ _tx_buffer->_aucBuffer [_tx_buffer->_iHead ] = uc_data;
151+ _tx_buffer->_iHead = l;
152+ // Make sure TX interrupt is enabled
153+ _pUart->UART_IER = UART_IER_TXRDY;
152154 }
153155 else
154156 {
155- // Send character
156- _pUart->UART_THR = uc_data ;
157+ // Bypass buffering and send character directly
158+ _pUart->UART_THR = uc_data;
157159 }
158160 return 1 ;
159161}
@@ -162,28 +164,28 @@ void UARTClass::IrqHandler( void )
162164{
163165 uint32_t status = _pUart->UART_SR ;
164166
165- // Did we receive data ?
167+ // Did we receive data?
166168 if ((status & UART_SR_RXRDY) == UART_SR_RXRDY)
167169 _rx_buffer->store_char (_pUart->UART_RHR );
168170
169- // Do we need to keep sending data?
171+ // Do we need to keep sending data?
170172 if ((status & UART_SR_TXRDY) == UART_SR_TXRDY)
171173 {
172- if (_tx_buffer->_iTail != _tx_buffer->_iHead ) { // just in case
173- _pUart->UART_THR = _tx_buffer->_aucBuffer [_tx_buffer->_iTail ];
174- _tx_buffer->_iTail = (unsigned int )(_tx_buffer->_iTail + 1 ) % SERIAL_BUFFER_SIZE;
175- }
176- else
177- {
178- _pUart->UART_IDR = UART_IDR_TXRDY; // mask off transmit interrupt so we don't get it anymore
179- }
174+ if (_tx_buffer->_iTail != _tx_buffer->_iHead ) {
175+ _pUart->UART_THR = _tx_buffer->_aucBuffer [_tx_buffer->_iTail ];
176+ _tx_buffer->_iTail = (unsigned int )(_tx_buffer->_iTail + 1 ) % SERIAL_BUFFER_SIZE;
177+ }
178+ else
179+ {
180+ // Mask off transmit interrupt so we don't get it anymore
181+ _pUart->UART_IDR = UART_IDR_TXRDY;
182+ }
180183 }
181184
182185 // Acknowledge errors
183- if ((status & UART_SR_OVRE) == UART_SR_OVRE ||
184- (status & UART_SR_FRAME) == UART_SR_FRAME)
186+ if ((status & UART_SR_OVRE) == UART_SR_OVRE || (status & UART_SR_FRAME) == UART_SR_FRAME)
185187 {
186- // TODO: error reporting outside ISR
188+ // TODO: error reporting outside ISR
187189 _pUart->UART_CR |= UART_CR_RSTSTA;
188190 }
189191}
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