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torvaldstorvalds
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Merge tag 'spi-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown: "This has been a fairly quiet release for SPI, though it is likely that the next release will have some big changes as there's some preparatory work for multiple chip select support gone in - the rest of the code is on the list but will need to be rebased onto -rc1. Otherwise there's a couple of new tunables for chip select timings, some new devices and smaller device specific updates and fixes. - Support for configuring the hold and minimum inactive times for chip selects. - Beginnings of support for supporting devices which have multiple chip selects on a single device. - Support for newer Broadcom HSSPI and Intel controllers, Silicon Labs EM3581 and SI3210" * tag 'spi-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (67 commits) spi: dt-bindings: qcom,spi-qcom-qspi: document OPP and power-domains spi: spidev: drop the incorrect notice from Kconfig spi: bcm63xx-hsspi: fix error code in probe spi: bcmbca-hsspi: Fix error code in probe() function spi: synquacer: Fix timeout handling in synquacer_spi_transfer_one() spi: intel: Check number of chip selects after reading the descriptor spi: xilinx: add force_irq for QSPI mode spi: spi-st-ssc: convert to DT schema spi: Reorder fields in 'struct spi_transfer' spi: cadence-quadspi: use STIG mode for small reads spi: cadence-quadspi: setup ADDR Bits in cmd reads spi: cadence-quadspi: Add flag for direct mode writes spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion MAINTAINERS: Remove file reference for Broadcom Broadband SoC HS SPI driver entry spi: bcm63xx-hsspi: bcmbca-hsspi: fix _be16 type usage MAINTAINERS: Add entry for Broadcom Broadband SoC HS SPI drivers spi: bcmbca-hsspi: Add driver for newer HSSPI controller spi: bcm63xx-hsspi: Disable spi mem dual io read op support spi: spi-mem: Allow controller supporting mem_ops without exec_op spi: bcm63xx-hsspi: Add prepend mode support ...
2 parents 0175ec3 + de82c25 commit 13e574b

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‎Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml‎

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title: Allwinner A10 SPI Controller
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allOf:
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- $ref: "spi-controller.yaml"
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- $ref: spi-controller.yaml
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>

‎Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml‎

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title: Allwinner A31 SPI Controller
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allOf:
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- $ref: "spi-controller.yaml"
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- $ref: spi-controller.yaml
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>

‎Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml‎

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# Copyright 2019 BayLibre, SAS
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/spi/amlogic,meson-gx-spicc.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/spi/amlogic,meson-gx-spicc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic Meson SPI Communication Controller
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maxItems: 2
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allOf:
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- $ref: "spi-controller.yaml#"
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- $ref: spi-controller.yaml#
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- if:
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properties:
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compatible:
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examples:
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- |
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spi@c1108d80 {
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compatible = "amlogic,meson-gx-spicc";
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reg = <0xc1108d80 0x80>;
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interrupts = <112>;
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clocks = <&clk81>;
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clock-names = "core";
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#address-cells = <1>;
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#size-cells = <0>;
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display@0 {
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compatible = "lg,lg4573";
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spi-max-frequency = <1000000>;
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reg = <0>;
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};
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compatible = "amlogic,meson-gx-spicc";
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reg = <0xc1108d80 0x80>;
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interrupts = <112>;
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clocks = <&clk81>;
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clock-names = "core";
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#address-cells = <1>;
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#size-cells = <0>;
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display@0 {
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compatible = "lg,lg4573";
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spi-max-frequency = <1000000>;
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reg = <0>;
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};
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};

‎Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml‎

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# Copyright 2019 BayLibre, SAS
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic Meson SPI Flash Controller
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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allOf:
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- $ref: "spi-controller.yaml#"
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- $ref: spi-controller.yaml#
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description: |
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The Meson SPIFC is a controller optimized for communication with SPI
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examples:
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- |
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spi@c1108c80 {
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compatible = "amlogic,meson6-spifc";
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reg = <0xc1108c80 0x80>;
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clocks = <&clk81>;
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#address-cells = <1>;
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#size-cells = <0>;
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flash: flash@0 {
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compatible = "spansion,m25p80", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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};
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compatible = "amlogic,meson6-spifc";
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reg = <0xc1108c80 0x80>;
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clocks = <&clk81>;
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#address-cells = <1>;
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#size-cells = <0>;
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flash: flash@0 {
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compatible = "spansion,m25p80", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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};
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};

‎Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml‎

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SPI) of the AST2400, AST2500 and AST2600 SOCs.
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allOf:
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- $ref: "spi-controller.yaml#"
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- $ref: spi-controller.yaml#
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properties:
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compatible:
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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flash@0 {
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reg = < 0 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <2>;
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reg = < 0 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <2>;
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};
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flash@1 {
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reg = < 1 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <2>;
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reg = < 1 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <2>;
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};
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flash@2 {
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reg = < 2 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <2>;
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reg = < 2 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <2>;
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};
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};

‎Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml‎

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom Broadband SoC High Speed SPI controller
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maintainers:
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- William Zhang <william.zhang@broadcom.com>
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- Kursad Oney <kursad.oney@broadcom.com>
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- Jonas Gorski <jonas.gorski@gmail.com>
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description: |
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Broadcom Broadband SoC supports High Speed SPI master controller since the
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early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0
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controller was carried over to recent ARM based chips, such as BCM63138,
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BCM4908 and BCM6858. The old MIPS based chip should continue to use the
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brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required to
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use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as
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defined below to match the specific chip along with ip revision info.
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This rev 1.0 controller has a limitation that can not keep the chip select line
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active between the SPI transfers within the same SPI message. This can
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terminate the transaction to some SPI devices prematurely. The issue can be
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worked around by either the controller's prepend mode or using the dummy chip
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select workaround. Driver automatically picks the suitable mode based on
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transfer type so it is transparent to the user.
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The newer SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI
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controller rev 1.1 that add the capability to allow the driver to control chip
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select explicitly. This solves the issue in the old controller.
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properties:
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compatible:
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oneOf:
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- const: brcm,bcm6328-hsspi
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- items:
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- enum:
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- brcm,bcm47622-hsspi
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- brcm,bcm4908-hsspi
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- brcm,bcm63138-hsspi
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- brcm,bcm63146-hsspi
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- brcm,bcm63148-hsspi
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- brcm,bcm63158-hsspi
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- brcm,bcm63178-hsspi
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- brcm,bcm6846-hsspi
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- brcm,bcm6856-hsspi
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- brcm,bcm6858-hsspi
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- brcm,bcm6878-hsspi
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- const: brcm,bcmbca-hsspi-v1.0
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- items:
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- enum:
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- brcm,bcm4912-hsspi
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- brcm,bcm6756-hsspi
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- brcm,bcm6813-hsspi
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- brcm,bcm6855-hsspi
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- const: brcm,bcmbca-hsspi-v1.1
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reg:
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items:
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- description: main registers
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- description: miscellaneous control registers
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minItems: 1
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reg-names:
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items:
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- const: hsspi
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- const: spim-ctrl
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minItems: 1
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clocks:
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items:
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- description: SPI master reference clock
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- description: SPI master pll clock
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clock-names:
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items:
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- const: hsspi
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- const: pll
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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allOf:
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- $ref: spi-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- brcm,bcm6328-hsspi
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- brcm,bcmbca-hsspi-v1.0
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then:
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properties:
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reg:
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maxItems: 1
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reg-names:
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maxItems: 1
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else:
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properties:
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reg:
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minItems: 2
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maxItems: 2
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reg-names:
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minItems: 2
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maxItems: 2
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required:
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- reg-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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spi@ff801000 {
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compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1";
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reg = <0xff801000 0x1000>,
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<0xff802610 0x4>;
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reg-names = "hsspi", "spim-ctrl";
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&hsspi>, <&hsspi_pll>;
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clock-names = "hsspi", "pll";
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num-cs = <8>;
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#address-cells = <1>;
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#size-cells = <0>;
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};

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