diff --git a/docs/projects/admx100x_evb/admx100x_hdl_block_diagram.svg b/docs/projects/admx100x_evb/admx100x_hdl_block_diagram.svg new file mode 100644 index 0000000000..a349aa3c66 --- /dev/null +++ b/docs/projects/admx100x_evb/admx100x_hdl_block_diagram.svg @@ -0,0 +1,1733 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +   +   + +   +   +   + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +   + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + GPIO + admx100x_sync_mode + admx100x_en + admx100x_cal + admx100x_spi_miso + admx100x_spi_sclk + admx100x_spi_cs_0 + admx100x_spi_cs_1 + admx100x_spi_mosi + admx100x_trig + admx100x_dac_ldac + admx100x_reset + admx100x_ready + admx100x_valid + admx100x_ot + I2C + Interrupts + Timer + + FMC CONNECTOR + + ARM + Zynq SoC + ZedBoard + + + + ADMX100x-FMCZ + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/projects/admx100x_evb/index.rst b/docs/projects/admx100x_evb/index.rst new file mode 100644 index 0000000000..c7baf4d776 --- /dev/null +++ b/docs/projects/admx100x_evb/index.rst @@ -0,0 +1,213 @@ +.. _admx100x_evb: + +ADMX100X-EVB HDL project +=============================================================================== + +Overview +------------------------------------------------------------------------------- + +The :adi:`EVAL-ADMX1001 ` and :adi:`EVAL-ADMX1002 ` +modules are ultra-low-distortion, low-noise signal generators. They support output +frequencies up to 40 kHz when the digital pre-distortion (DPD) algorithm is disabled, +and up to 20 kHz with DPD enabled while maintaining a typical total harmonic distortion +(THD) of −130 dB at 1 kHz. The ADMX1001 includes a built-in acquisition channel that +enables simultaneous generation and capture of differential signals, making it ideal +for characterization and closed-loop evaluation of high-performance ADCs, audio converters, +and precision sensing systems. The integrated DPD algorithm minimizes distortion typically +introduced by DAC and amplifier stages, enabling the generation of extremely clean test +signals for precision measurement applications. The ADMX1002 focuses solely on high-fidelity +signal generation, providing a streamlined solution for setups where local signal acquisition +is not required. + +Supported boards +------------------------------------------------------------------------------- + +- :adi:`EVAL-ADMX1001 ` +- :adi:`EVAL-ADMX1002 ` + +Supported devices +------------------------------------------------------------------------------- + +- :adi:`AD5683R` + +Supported carriers +------------------------------------------------------------------------------- + +.. list-table:: + :widths: 35 35 30 + :header-rows: 1 + + * - Evaluation board + - Carrier + - FMC slot + * - EVAL-ADMX1001 + - `ZedBoard `__ + - FMC LPC + * - EVAL-ADMX1002 + - `ZedBoard `__ + - FMC LPC + +Block design +------------------------------------------------------------------------------- + +.. warning:: + + The VADJ for the Zedboard must be set to 3.3V. + +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The data path and clock domains are depicted in the below diagram: + +.. image:: admx100x_hdl_block_diagram.svg + :width: 800 + :align: center + :alt: ADMX100X/ZedBoard block diagram + +SPI connections +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 1 + + * - SPI type + - SPI manager instance + - SPI subordinate + - CS + * - PS + - SPI 0 + - CS_FPGA + - 0 + * - PS + - SPI 1 + - CS_DAC + - 1 + +GPIOs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 2 + + * - GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + * - + - (from FPGA view) + - + - Zynq-7000 + * - ADMX100X_SYNC_MODE + - OUT + - 34 + - 88 + * - ADMX100X_EN + - OUT + - 35 + - 89 + * - ADMX100X_CAL + - OUT + - 38 + - 92 + * - ADMX100X_TRIG + - OUT + - 40 + - 94 + * - ADMX100X_DAC_LDAC + - OUT + - 39 + - 93 + * - ADMX100X_RESET + - OUT + - 33 + - 87 + * - ADMX100X_READY + - IN + - 36 + - 90 + * - ADMX100X_VALID + - IN + - 37 + - 91 + * - ADMX100X_OT + - IN + - 32 + - 86 + +Building the HDL project +------------------------------------------------------------------------------- + +The design is built upon ADI's generic HDL reference design framework. +ADI distributes the bit/elf files of these projects as part of the +:dokuwiki:`ADI Kuiper Linux `. +If you want to build the sources, ADI makes them available on the +:git-hdl:`HDL repository `. To get the source you must +`clone `__ +the HDL repository. + +**Linux/Cygwin/WSL** + +Building the ZedBoard project: + +.. shell:: + + $cd hdl/projects/admx100xevb/zed + $make + +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. + +Resources +------------------------------------------------------------------------------- + +Hardware related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Product datasheets: + + - :adi:`AD5683R` + +HDL related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-hdl:`ADMX100X-EVB HDL project source code ` + +.. list-table:: + :widths: 30 35 35 + :header-rows: 1 + + * - IP name + - Source code link + - Documentation link + * - AXI_AD777x + - :git-hdl:`library/axi_ad777x` + - :ref:`axi_ad777x` + * - AXI_CLKGEN + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` + * - AXI_DMAC + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` + * - AXI_HDMI_TX + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` + * - AXI_I2S_ADI + - :git-hdl:`library/axi_i2s_adi` + - — + * - AXI_SPDIF_TX + - :git-hdl:`library/axi_spdif_tx` + - — + * - AXI_SYSID + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` + * - SYSID_ROM + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` + * - UTIL_I2C_MIXER + - :git-hdl:`library/util_i2c_mixer` + - — + +.. include:: ../common/more_information.rst + +.. include:: ../common/support.rst diff --git a/projects/admx100x_evb/Makefile b/projects/admx100x_evb/Makefile new file mode 100644 index 0000000000..68a7ed005c --- /dev/null +++ b/projects/admx100x_evb/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/admx100x_evb/README.md b/projects/admx100x_evb/README.md new file mode 100755 index 0000000000..93176aa698 --- /dev/null +++ b/projects/admx100x_evb/README.md @@ -0,0 +1,18 @@ +# ADMX100X-EVB HDL Project + +- Evaluation boards product page: + - [EVAL-ADMX1001](https://www.analog.com/eval-admx1001) + - [EVAL-ADMX1002](https://www.analog.com/eval-admx1002) +- System documentation: TO BE ADDED +- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/admx100xevb/index.html +- Evaluation board VADJ: 3.3V + +## Supported parts + +| Part name | Description | +|------------------------------------------------|---------------------------------------------------------------------------------| +| [AD5683R](https://www.analog.com/ad5683r) | Tiny 16-Bit SPI nanoDAC+, with ±2 (16-Bit) LSB INL and 2 ppm/°C Reference | + +## Building the project + +Please enter the folder for the FPGA carrier you want to use and read the README.md. diff --git a/projects/admx100x_evb/common/admx1001.txt b/projects/admx100x_evb/common/admx1001.txt new file mode 100644 index 0000000000..e5de382b46 --- /dev/null +++ b/projects/admx100x_evb/common/admx1001.txt @@ -0,0 +1,27 @@ +FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination + +# admx1001 + +C10 FMC_LA06_P ACQ_SYNC_IN_FMC LVCMOS33 #N/A +D8 FMC_LA01_CC_P ACQ_SCLK LVCMOS33 #N/A +D12 FMC_LA05_N ACQ_DRDY LVCMOS33 #N/A +G6 FMC_LA00_CC_P ACQ_MCLK LVCMOS33 #N/A +G9 FMC_LA03_P ACQ_SDI LVCMOS33 #N/A +G15 FMC_LA12_P ACQ_RESET LVCMOS33 #N/A +H7 FMC_LA02_P ACQ_DOUT LVCMOS33 #N/A +H11 FMC_LA04_N ACQ_CS LVCMOS33 #N/A +D17 FMC_LA13_P SPI_SCLK admx100x_spi_sclk LVCMOS33 #N/A +C19 FMC_LA14_N SPI_MISO admx100x_spi_miso LVCMOS33 #N/A +H19 FMC_LA15_P SPI_MOSI admx100x_spi_mosi LVCMOS33 #N/A +G27 FMC_LA25_P SPI_CS_DAC admx100x_spi_cs_1 LVCMOS33 #N/A +G18 FMC_LA16_P SPI_SS admx100x_spi_cs_0 LVCMOS33 #N/A +G24 FMC_LA22_P DAC_RESET admx100x_reset LVCMOS33 #N/A +C14 FMC_LA10_P EN admx100x_en LVCMOS33 #N/A +C26 FMC_LA27_P CAL admx100x_cal LVCMOS33 #N/A +C30 FMC_SCL SCL admx100x_scl LVCMOS33 #N/A +D14 FMC_LA09_P READY admx100x_ready LVCMOS33 #N/A +G12 FMC_LA08_P VALID admx100x_valid LVCMOS33 #N/A +G21 FMC_LA20_P DAC_LDAC admx100x_dac_ldac LVCMOS33 #N/A +H13 FMC_LA07_P TRIG admx100x_trig LVCMOS33 #N/A +H16 FMC_LA11_P OT admx100x_ot LVCMOS33 #N/A +H22 FMC_LA19_P SYNC_MODE admx100x_sync_mode LVCMOS33 #N/A \ No newline at end of file diff --git a/projects/admx100x_evb/zed/Makefile b/projects/admx100x_evb/zed/Makefile new file mode 100644 index 0000000000..0046bafac5 --- /dev/null +++ b/projects/admx100x_evb/zed/Makefile @@ -0,0 +1,24 @@ +#################################################################################### +## Copyright (c) 2018 - 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := admx100x_evb_zed + +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_data_clk.v +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer + +include ../../scripts/project-xilinx.mk diff --git a/projects/admx100x_evb/zed/README.md b/projects/admx100x_evb/zed/README.md new file mode 100644 index 0000000000..ed425b60dc --- /dev/null +++ b/projects/admx100x_evb/zed/README.md @@ -0,0 +1,12 @@ + + +# ADMX100X-EVB/ZED HDL Project + +- VADJ with which it was tested in hardware: 3.3V + +## Building the project + +``` +cd projects/admx100x_evb/zed +make +``` diff --git a/projects/admx100x_evb/zed/system_bd.tcl b/projects/admx100x_evb/zed/system_bd.tcl new file mode 100644 index 0000000000..f98962100d --- /dev/null +++ b/projects/admx100x_evb/zed/system_bd.tcl @@ -0,0 +1,14 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file diff --git a/projects/admx100x_evb/zed/system_constr.xdc b/projects/admx100x_evb/zed/system_constr.xdc new file mode 100644 index 0000000000..055953a9f2 --- /dev/null +++ b/projects/admx100x_evb/zed/system_constr.xdc @@ -0,0 +1,52 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# SPI interface + +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports admx100x_spi_sclk]; ## D17 FMC_LA13_P +set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS33} [get_ports admx100x_spi_miso]; ## C19 FMC_LA14_N +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports admx100x_spi_mosi]; ## H19 FMC_LA15_P +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS33} [get_ports admx100x_spi_cs_0]; ## G18 FMC_LA16_P CS_FPGA +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33} [get_ports admx100x_spi_cs_1]; ## G27 FMC_LA25_P CS_DAC + +# reset and GPIO signal + +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS33} [get_ports admx100x_reset]; ##G24 FMC_LA22_P DAC_RESET +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports admx100x_en]; ##C14 FMC_LA10_P +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33} [get_ports admx100x_ready]; ##D14 FMC_LA09_P +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS33} [get_ports admx100x_valid]; ##G12 FMC_LA08_P +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports admx100x_cal]; ##C26 FMC_LA27_P +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS33} [get_ports admx100x_dac_ldac]; ##G21 FMC_LA20_P +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports admx100x_trig]; ##H13 FMC_LA07_P +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports admx100x_ot]; ##H16 FMC_LA11_P + +# syncronization +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports admx100x_sync_mode]; ##H22 FMC_LA19_P SYNC_MODE + +# set IOSTANDARD according to VADJ 3.3V + +set_property -dict {IOSTANDARD LVCMOS33} [get_ports otg_vbusoc] + +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[0]] ; ## BTNC +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[1]] ; ## BTND +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[2]] ; ## BTNL +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[3]] ; ## BTNR +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[4]] ; ## BTNU + +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[11]] ; ## SW0 +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[12]] ; ## SW1 +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[13]] ; ## SW2 +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[14]] ; ## SW3 +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[15]] ; ## SW4 +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[16]] ; ## SW5 +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[17]] ; ## SW6 +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[18]] ; ## SW7 + +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0 +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1 +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2 +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3 + +set_property -dict {IOSTANDARD LVCMOS33} [get_ports gpio_bd[31]] ; ## OTG-RESETN diff --git a/projects/admx100x_evb/zed/system_project.tcl b/projects/admx100x_evb/zed/system_project.tcl new file mode 100644 index 0000000000..f995f79231 --- /dev/null +++ b/projects/admx100x_evb/zed/system_project.tcl @@ -0,0 +1,19 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project admx100x_evb_zed + +adi_project_files admx100x_evb_zed [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ + "system_constr.xdc" \ + "system_top.v"] + +adi_project_run admx100x_evb_zed diff --git a/projects/admx100x_evb/zed/system_top.v b/projects/admx100x_evb/zed/system_top.v new file mode 100755 index 0000000000..8279607bb8 --- /dev/null +++ b/projects/admx100x_evb/zed/system_top.v @@ -0,0 +1,226 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output spdif, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + input admx100x_sync_mode, + input admx100x_en, + input admx100x_cal, + input admx100x_trig, + inout admx100x_dac_ldac, + inout admx100x_reset, + output admx100x_ready, + output admx100x_valid, + output admx100x_ot, + + input admx100x_spi_miso, + output admx100x_spi_mosi, + output admx100x_spi_sclk, + output admx100x_spi_cs_0, + output admx100x_spi_cs_1 +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + // gpio assign + + assign admx100x_sync_mode = gpio_o[34]; + assign admx100x_en = gpio_o[35]; + assign admx100x_cal = gpio_o[38]; + assign admx100x_trig = gpio_o[40]; + assign admx100x_dac_ldac = gpio_o[39]; + assign admx100x_reset = gpio_o[33]; + assign gpio_i[36] = admx100x_ready; + assign gpio_i[37] = admx100x_valid; + assign gpio_i[32] = admx100x_ot; + + assign gpio_i[63:41] = gpio_o[63:41]; + + // instantiations + + ad_iobuf #( + .DATA_WIDTH (32) + ) i_iobuf ( + .dio_t (gpio_t[31:0]), + .dio_i (gpio_o[31:0]), + .dio_o (gpio_i[31:0]), + .dio_p (gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_scl ( + .dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i (iic_mux_scl_o_s), + .dio_o (iic_mux_scl_i_s), + .dio_p (iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_sda ( + .dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i (iic_mux_sda_o_s), + .dio_o (iic_mux_sda_i_s), + .dio_p (iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + + .spdif (spdif), + + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + + .otg_vbusoc (otg_vbusoc), + + .spi0_clk_i (1'b0), + .spi0_clk_o (admx100x_spi_sclk), + .spi0_csn_0_o (admx100x_spi_cs_0), + .spi0_csn_1_o (admx100x_spi_cs_1), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (admx100x_spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (admx100x_spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o ()); + +endmodule