From d04971995d106d7a920d692578b3f39a80fb4421 Mon Sep 17 00:00:00 2001 From: Laez Barbosa Date: Fri, 10 Oct 2025 10:45:14 -0300 Subject: [PATCH 1/6] library/spi_engine: rename xilinx script Signed-off-by: Laez Barbosa --- docs/library/spi_engine/tutorial.rst | 4 ++-- docs/user_guide/ip_cores/use_adi_ips.rst | 4 ++-- .../{spi_engine.tcl => spi_engine_xilinx.tcl} | 16 +++++++++++++++- projects/ad4052_ardz/common/ad4052_bd.tcl | 2 +- projects/ad4052_ardz/coraz7s/Makefile | 2 +- projects/ad4134_fmc/common/ad4134_bd.tcl | 2 +- projects/ad4134_fmc/zed/Makefile | 2 +- projects/ad4170_asdz/common/ad4170_asdz_bd.tcl | 2 +- projects/ad4170_asdz/coraz7s/Makefile | 2 +- projects/ad4630_fmc/common/ad463x_bd.tcl | 2 +- projects/ad4630_fmc/zed/Makefile | 2 +- projects/ad469x_evb/common/ad469x_bd.tcl | 2 +- projects/ad469x_evb/coraz7s/Makefile | 2 +- projects/ad469x_evb/zed/Makefile | 2 +- projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl | 2 +- projects/ad57xx_ardz/coraz7s/Makefile | 2 +- projects/ad7134_fmc/common/ad7134_bd.tcl | 2 +- projects/ad7134_fmc/zed/Makefile | 2 +- projects/ad738x_fmc/common/ad738x_bd.tcl | 2 +- projects/ad738x_fmc/zed/Makefile | 2 +- projects/ad7606x_fmc/common/ad7606x_bd.tcl | 2 +- projects/ad7606x_fmc/zed/Makefile | 2 +- projects/ad7616_sdz/common/ad7616_bd.tcl | 2 +- projects/ad7616_sdz/zed/Makefile | 2 +- projects/ad77681evb/common/ad77681evb_bd.tcl | 2 +- projects/ad77681evb/zed/Makefile | 2 +- projects/adaq7980_sdz/common/adaq7980_bd.tcl | 12 ++++++------ projects/adaq7980_sdz/zed/Makefile | 2 +- projects/cn0363/common/cn0363_bd.tcl | 2 +- projects/cn0363/zed/Makefile | 2 +- projects/cn0540/common/cn0540_bd.tcl | 2 +- projects/cn0540/coraz7s/Makefile | 2 +- projects/cn0561/common/cn0561_bd.tcl | 2 +- projects/cn0561/coraz7s/Makefile | 2 +- projects/cn0561/zed/Makefile | 2 +- projects/pulsar_adc/common/pulsar_adc_bd.tcl | 2 +- projects/pulsar_adc/coraz7s/Makefile | 2 +- projects/pulsar_adc/zed/Makefile | 2 +- 38 files changed, 59 insertions(+), 45 deletions(-) rename library/spi_engine/scripts/{spi_engine.tcl => spi_engine_xilinx.tcl} (86%) diff --git a/docs/library/spi_engine/tutorial.rst b/docs/library/spi_engine/tutorial.rst index 3f892fd3820..0045767bbd4 100644 --- a/docs/library/spi_engine/tutorial.rst +++ b/docs/library/spi_engine/tutorial.rst @@ -68,7 +68,7 @@ SPI Engine hierarchy instantiation The SPI Engine can be implemented in two ways, either by placing and connecting each IP individually or by using the function provided by the -:git-hdl:`library/spi_engine/scripts/spi_engine.tcl` script. +:git-hdl:`library/spi_engine/scripts/spi_engine_xilinx.tcl` script. Using the script ensures that the correct connections are being made and that the IP cores will receive the correct parameter configuration since certain @@ -103,7 +103,7 @@ Configuration tcl code and result below: .. code:: tcl - source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl + source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 32 set async_spi_clk 1 diff --git a/docs/user_guide/ip_cores/use_adi_ips.rst b/docs/user_guide/ip_cores/use_adi_ips.rst index a8865fe4858..86e16436106 100644 --- a/docs/user_guide/ip_cores/use_adi_ips.rst +++ b/docs/user_guide/ip_cores/use_adi_ips.rst @@ -158,11 +158,11 @@ In order to use it into your own project, you will have to add all of its compon For this example, the code shown here is from the ad4630_fmc project: :git-hdl:`projects/ad4630_fmc/common/ad463x_bd.tcl` -Let's start with sourcing the spi_engine.tcl script inside your ``_db.tcl``. +Let's start with sourcing the spi_engine_xilinx.tcl script inside your ``_db.tcl``. .. code:: tcl - source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl + source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl The SPI engine has 4 modules: execution, interconnect, regmap and offload. diff --git a/library/spi_engine/scripts/spi_engine.tcl b/library/spi_engine/scripts/spi_engine_xilinx.tcl similarity index 86% rename from library/spi_engine/scripts/spi_engine.tcl rename to library/spi_engine/scripts/spi_engine_xilinx.tcl index 0b22305e30a..d4d7852aa7e 100644 --- a/library/spi_engine/scripts/spi_engine.tcl +++ b/library/spi_engine/scripts/spi_engine_xilinx.tcl @@ -3,7 +3,21 @@ ### SPDX short identifier: ADIBSD ############################################################################### -proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0} {sdo_streaming 0} {cmd_mem_addr_width 4} {data_mem_addr_width 4} {sdi_fifo_addr_width 5} {sdo_fifo_addr_width 5} {sync_fifo_addr_width 4} {cmd_fifo_addr_width 4}} { +proc spi_engine_create {{name "spi_engine"} + {data_width 32} + {async_spi_clk 1} + {num_cs 1} + {num_sdi 1} + {num_sdo 1} + {sdi_delay 0} + {echo_sclk 0} + {sdo_streaming 0} + {cmd_mem_addr_width 4} + {data_mem_addr_width 4} + {sdi_fifo_addr_width 5} + {sdo_fifo_addr_width 5} + {sync_fifo_addr_width 4} + {cmd_fifo_addr_width 4}} { puts "echo_sclk: $echo_sclk" create_bd_cell -type hier $name diff --git a/projects/ad4052_ardz/common/ad4052_bd.tcl b/projects/ad4052_ardz/common/ad4052_bd.tcl index 0b01a486e02..24903ac5547 100644 --- a/projects/ad4052_ardz/common/ad4052_bd.tcl +++ b/projects/ad4052_ardz/common/ad4052_bd.tcl @@ -7,7 +7,7 @@ create_bd_port -dir O adc_cnv create_bd_port -dir I adc_gp1_n create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adc_spi -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 32 set async_spi_clk 1 diff --git a/projects/ad4052_ardz/coraz7s/Makefile b/projects/ad4052_ardz/coraz7s/Makefile index 7119cb108f6..f65a0c44d29 100644 --- a/projects/ad4052_ardz/coraz7s/Makefile +++ b/projects/ad4052_ardz/coraz7s/Makefile @@ -11,7 +11,7 @@ M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_clkgen diff --git a/projects/ad4134_fmc/common/ad4134_bd.tcl b/projects/ad4134_fmc/common/ad4134_bd.tcl index 255ef9292d4..f2deff81d47 100644 --- a/projects/ad4134_fmc/common/ad4134_bd.tcl +++ b/projects/ad4134_fmc/common/ad4134_bd.tcl @@ -8,7 +8,7 @@ create_bd_port -dir O ad4134_odr # create a SPI Engine architecture for ADC -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 32 set async_spi_clk 1 diff --git a/projects/ad4134_fmc/zed/Makefile b/projects/ad4134_fmc/zed/Makefile index aa3cf0b0cb6..07a6c757b92 100755 --- a/projects/ad4134_fmc/zed/Makefile +++ b/projects/ad4134_fmc/zed/Makefile @@ -9,7 +9,7 @@ PROJECT_NAME := ad4134_fmc_zed M_DEPS += ../common/ad4134_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_clkgen diff --git a/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl b/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl index a89e1a34230..619b79d17b9 100644 --- a/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl +++ b/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl @@ -7,7 +7,7 @@ create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 a create_bd_port -dir I adc_data_ready -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 32 set async_spi_clk 1 diff --git a/projects/ad4170_asdz/coraz7s/Makefile b/projects/ad4170_asdz/coraz7s/Makefile index 63dcfe38c68..c2691112f8b 100644 --- a/projects/ad4170_asdz/coraz7s/Makefile +++ b/projects/ad4170_asdz/coraz7s/Makefile @@ -12,7 +12,7 @@ M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_edge_detect.v diff --git a/projects/ad4630_fmc/common/ad463x_bd.tcl b/projects/ad4630_fmc/common/ad463x_bd.tcl index 0be531bfbc3..3687f4a1cad 100644 --- a/projects/ad4630_fmc/common/ad463x_bd.tcl +++ b/projects/ad4630_fmc/common/ad463x_bd.tcl @@ -3,7 +3,7 @@ ### SPDX short identifier: ADIBSD ############################################################################### -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl # system level parameters set NUM_OF_SDI $ad_project_params(NUM_OF_SDI) set CAPTURE_ZONE $ad_project_params(CAPTURE_ZONE) diff --git a/projects/ad4630_fmc/zed/Makefile b/projects/ad4630_fmc/zed/Makefile index 8f0b0a9fdc9..991d5161f03 100644 --- a/projects/ad4630_fmc/zed/Makefile +++ b/projects/ad4630_fmc/zed/Makefile @@ -16,7 +16,7 @@ M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../../library/xilinx/common/ad_data_clk.v M_DEPS += ../../../library/util_cdc/sync_bits.v -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_edge_detect.v diff --git a/projects/ad469x_evb/common/ad469x_bd.tcl b/projects/ad469x_evb/common/ad469x_bd.tcl index 93c71dd47db..6e564aa2d70 100644 --- a/projects/ad469x_evb/common/ad469x_bd.tcl +++ b/projects/ad469x_evb/common/ad469x_bd.tcl @@ -14,7 +14,7 @@ create_bd_port -dir O ad469x_spi_cnv create_bd_port -dir I ad469x_spi_busy create_bd_port -dir I gpio_cnv -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 32 set async_spi_clk 1 diff --git a/projects/ad469x_evb/coraz7s/Makefile b/projects/ad469x_evb/coraz7s/Makefile index 62da12167fa..6ae19e870c1 100644 --- a/projects/ad469x_evb/coraz7s/Makefile +++ b/projects/ad469x_evb/coraz7s/Makefile @@ -12,7 +12,7 @@ M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_edge_detect.v diff --git a/projects/ad469x_evb/zed/Makefile b/projects/ad469x_evb/zed/Makefile index 1e70af9c770..fddda268192 100644 --- a/projects/ad469x_evb/zed/Makefile +++ b/projects/ad469x_evb/zed/Makefile @@ -11,7 +11,7 @@ M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_edge_detect.v diff --git a/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl b/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl index 35330a82881..2055e9bd180 100644 --- a/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl +++ b/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl @@ -9,7 +9,7 @@ create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 a # create a SPI Engine architecture for the DAC -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 32 set async_spi_clk 1 diff --git a/projects/ad57xx_ardz/coraz7s/Makefile b/projects/ad57xx_ardz/coraz7s/Makefile index a1ae88a5f87..4c2ea7e2850 100644 --- a/projects/ad57xx_ardz/coraz7s/Makefile +++ b/projects/ad57xx_ardz/coraz7s/Makefile @@ -11,7 +11,7 @@ M_DEPS += ../common/ad57xx_ardz_bd.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_clkgen diff --git a/projects/ad7134_fmc/common/ad7134_bd.tcl b/projects/ad7134_fmc/common/ad7134_bd.tcl index a861bc3f70f..2c02bafc7ee 100644 --- a/projects/ad7134_fmc/common/ad7134_bd.tcl +++ b/projects/ad7134_fmc/common/ad7134_bd.tcl @@ -10,7 +10,7 @@ create_bd_port -dir O ad713x_sdpclk # create a SPI Engine architecture for the parallel data interface of AD713x # this design supports AD7132/AD7134/AD7136 -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 32 set async_spi_clk 1 diff --git a/projects/ad7134_fmc/zed/Makefile b/projects/ad7134_fmc/zed/Makefile index f89879abb73..1dad988a4d1 100644 --- a/projects/ad7134_fmc/zed/Makefile +++ b/projects/ad7134_fmc/zed/Makefile @@ -11,7 +11,7 @@ M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_edge_detect.v diff --git a/projects/ad738x_fmc/common/ad738x_bd.tcl b/projects/ad738x_fmc/common/ad738x_bd.tcl index b1a95a2d829..7838d10c705 100644 --- a/projects/ad738x_fmc/common/ad738x_bd.tcl +++ b/projects/ad738x_fmc/common/ad738x_bd.tcl @@ -13,7 +13,7 @@ puts "build parameter: NUM_OF_SDI: $NUM_OF_SDI" create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad738x_spi -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 32 set async_spi_clk 1 diff --git a/projects/ad738x_fmc/zed/Makefile b/projects/ad738x_fmc/zed/Makefile index 2707abbceee..aa9093a9c1c 100644 --- a/projects/ad738x_fmc/zed/Makefile +++ b/projects/ad738x_fmc/zed/Makefile @@ -13,7 +13,7 @@ M_DEPS += ../common/ad738x_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_clkgen diff --git a/projects/ad7606x_fmc/common/ad7606x_bd.tcl b/projects/ad7606x_fmc/common/ad7606x_bd.tcl index 2ea60699faf..5c17ae68ca4 100644 --- a/projects/ad7606x_fmc/common/ad7606x_bd.tcl +++ b/projects/ad7606x_fmc/common/ad7606x_bd.tcl @@ -114,7 +114,7 @@ switch $INTF { ad_connect $sys_cpu_clk spi_clkgen/clk # spi engine - source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl + source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 32 set async_spi_clk 1 diff --git a/projects/ad7606x_fmc/zed/Makefile b/projects/ad7606x_fmc/zed/Makefile index 6d8a0284a7a..1ddd84b7792 100644 --- a/projects/ad7606x_fmc/zed/Makefile +++ b/projects/ad7606x_fmc/zed/Makefile @@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_edge_detect.v diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl index d628377c6ef..3c9f60980c3 100644 --- a/projects/ad7616_sdz/common/ad7616_bd.tcl +++ b/projects/ad7616_sdz/common/ad7616_bd.tcl @@ -49,7 +49,7 @@ ad_connect busy_sync/out_bits busy_capture/signal_in if {$INTF == 1} { create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad7616_spi - source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl + source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 16 set async_spi_clk 1 diff --git a/projects/ad7616_sdz/zed/Makefile b/projects/ad7616_sdz/zed/Makefile index d8c2836366e..c086bed0fae 100644 --- a/projects/ad7616_sdz/zed/Makefile +++ b/projects/ad7616_sdz/zed/Makefile @@ -14,7 +14,7 @@ M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_edge_detect.v diff --git a/projects/ad77681evb/common/ad77681evb_bd.tcl b/projects/ad77681evb/common/ad77681evb_bd.tcl index 87db7c51c3a..4c39701d710 100644 --- a/projects/ad77681evb/common/ad77681evb_bd.tcl +++ b/projects/ad77681evb/common/ad77681evb_bd.tcl @@ -9,7 +9,7 @@ create_bd_port -dir I adc_data_ready # create a SPI Engine architecture for ADC -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 32 set async_spi_clk 1 diff --git a/projects/ad77681evb/zed/Makefile b/projects/ad77681evb/zed/Makefile index d7a6b04da3b..acf4b3d1bb0 100644 --- a/projects/ad77681evb/zed/Makefile +++ b/projects/ad77681evb/zed/Makefile @@ -11,7 +11,7 @@ M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../../library/xilinx/common/ad_data_clk.v -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_clkgen diff --git a/projects/adaq7980_sdz/common/adaq7980_bd.tcl b/projects/adaq7980_sdz/common/adaq7980_bd.tcl index 6f81d32e770..9dae03009ed 100644 --- a/projects/adaq7980_sdz/common/adaq7980_bd.tcl +++ b/projects/adaq7980_sdz/common/adaq7980_bd.tcl @@ -4,15 +4,15 @@ ############################################################################### create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adaq7980_spi -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 16 -set async_spi_clk 1 +set async_spi_clk 1 set num_cs 1 -set num_sdi 1 -set num_sdo 1 -set sdi_delay 1 -set echo_sclk 0 +set num_sdi 1 +set num_sdo 1 +set sdi_delay 1 +set echo_sclk 0 set hier_spi_engine spi_adaq7980_adc diff --git a/projects/adaq7980_sdz/zed/Makefile b/projects/adaq7980_sdz/zed/Makefile index 62e96ab0cdd..d013da5ffd4 100644 --- a/projects/adaq7980_sdz/zed/Makefile +++ b/projects/adaq7980_sdz/zed/Makefile @@ -10,7 +10,7 @@ M_DEPS += ../common/adaq7980_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_clkgen diff --git a/projects/cn0363/common/cn0363_bd.tcl b/projects/cn0363/common/cn0363_bd.tcl index a03302e3a3a..8e39141c73f 100644 --- a/projects/cn0363/common/cn0363_bd.tcl +++ b/projects/cn0363/common/cn0363_bd.tcl @@ -3,7 +3,7 @@ ### SPDX short identifier: ADIBSD ############################################################################### -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 spi diff --git a/projects/cn0363/zed/Makefile b/projects/cn0363/zed/Makefile index dc4dd1e3d9e..2d9719044d9 100644 --- a/projects/cn0363/zed/Makefile +++ b/projects/cn0363/zed/Makefile @@ -10,7 +10,7 @@ M_DEPS += ../common/cn0363_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_clkgen diff --git a/projects/cn0540/common/cn0540_bd.tcl b/projects/cn0540/common/cn0540_bd.tcl index 55f6d2c18fc..db8d5ce1510 100755 --- a/projects/cn0540/common/cn0540_bd.tcl +++ b/projects/cn0540/common/cn0540_bd.tcl @@ -14,7 +14,7 @@ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1. create_bd_port -dir I adc_data_ready -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 32 set async_spi_clk 1 diff --git a/projects/cn0540/coraz7s/Makefile b/projects/cn0540/coraz7s/Makefile index df8363921b7..e66bb98d76c 100755 --- a/projects/cn0540/coraz7s/Makefile +++ b/projects/cn0540/coraz7s/Makefile @@ -11,7 +11,7 @@ M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_clkgen diff --git a/projects/cn0561/common/cn0561_bd.tcl b/projects/cn0561/common/cn0561_bd.tcl index d0ecf3424a7..78d043b6201 100644 --- a/projects/cn0561/common/cn0561_bd.tcl +++ b/projects/cn0561/common/cn0561_bd.tcl @@ -8,7 +8,7 @@ create_bd_port -dir O cn0561_odr # create a SPI Engine architecture for ADC -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl set data_width 32 set async_spi_clk 1 diff --git a/projects/cn0561/coraz7s/Makefile b/projects/cn0561/coraz7s/Makefile index 55ffe32f286..b29332afe30 100644 --- a/projects/cn0561/coraz7s/Makefile +++ b/projects/cn0561/coraz7s/Makefile @@ -12,7 +12,7 @@ M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_edge_detect.v diff --git a/projects/cn0561/zed/Makefile b/projects/cn0561/zed/Makefile index 0d86cac130f..b590620a959 100755 --- a/projects/cn0561/zed/Makefile +++ b/projects/cn0561/zed/Makefile @@ -11,7 +11,7 @@ M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_edge_detect.v diff --git a/projects/pulsar_adc/common/pulsar_adc_bd.tcl b/projects/pulsar_adc/common/pulsar_adc_bd.tcl index eec33060ad5..7ee4c31dbaa 100644 --- a/projects/pulsar_adc/common/pulsar_adc_bd.tcl +++ b/projects/pulsar_adc/common/pulsar_adc_bd.tcl @@ -4,7 +4,7 @@ ############################################################################### create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 pulsar_adc_spi -source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl # If the ADC resolution <= 16, data_width is set 16 else 32 set data_width 32 diff --git a/projects/pulsar_adc/coraz7s/Makefile b/projects/pulsar_adc/coraz7s/Makefile index 870f8fe7fca..2ed88a3d1cd 100644 --- a/projects/pulsar_adc/coraz7s/Makefile +++ b/projects/pulsar_adc/coraz7s/Makefile @@ -11,7 +11,7 @@ M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_clkgen diff --git a/projects/pulsar_adc/zed/Makefile b/projects/pulsar_adc/zed/Makefile index 81bc32e9fbb..913f17a65a1 100644 --- a/projects/pulsar_adc/zed/Makefile +++ b/projects/pulsar_adc/zed/Makefile @@ -15,7 +15,7 @@ M_DEPS += ../common/pulsar_adc_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_clkgen From 81b1c44e34f2b4e22114eda659d94f0937bcfeb7 Mon Sep 17 00:00:00 2001 From: Laez Barbosa Date: Mon, 13 Oct 2025 12:51:20 -0300 Subject: [PATCH 2/6] library/spi_engine: add intel script Signed-off-by: Laez Barbosa --- .../spi_engine/scripts/spi_engine_intel.tcl | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 library/spi_engine/scripts/spi_engine_intel.tcl diff --git a/library/spi_engine/scripts/spi_engine_intel.tcl b/library/spi_engine/scripts/spi_engine_intel.tcl new file mode 100644 index 00000000000..b14bf8e1c35 --- /dev/null +++ b/library/spi_engine/scripts/spi_engine_intel.tcl @@ -0,0 +1,99 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +proc spi_engine_create {{name "spi_engine"} + {axi_clk} + {axi_reset} + {spi_clk} + {data_width 32} + {async_spi_clk 1} + {num_cs 1} + {num_sdi 1} + {num_sdo 1} + {sdi_delay 0} + {echo_sclk 0} + {sdo_streaming 0} + {cmd_mem_addr_width 4} + {data_mem_addr_width 4} + {sdi_fifo_addr_width 5} + {sdo_fifo_addr_width 5} + {sync_fifo_addr_width 4} + {cmd_fifo_addr_width 4}} { + + set execution "${name}_execution" + set axi_regmap "${name}_axi_regmap" + set offload "${name}_offload" + set interconnect "${name}_interconnect" + + add_instance $execution spi_engine_execution + set_instance_parameter_value $execution {NUM_OF_CS} $num_cs + set_instance_parameter_value $execution {DATA_WIDTH} $data_width + set_instance_parameter_value $execution {NUM_OF_SDI} $num_sdi + set_instance_parameter_value $execution {SDI_DELAY} $sdi_delay + set_instance_parameter_value $execution {ECHO_SCLK} $echo_sclk + set_instance_parameter_value $execution {SDO_DEFAULT} 1 + + add_instance $axi_regmap axi_spi_engine + set_instance_parameter_value $axi_regmap {ASYNC_SPI_CLK} $async_spi_clk + set_instance_parameter_value $axi_regmap {DATA_WIDTH} $data_width + set_instance_parameter_value $axi_regmap {MM_IF_TYPE} {0} + set_instance_parameter_value $axi_regmap {NUM_OF_SDI} $num_sdi + set_instance_parameter_value $axi_regmap {NUM_OFFLOAD} {1} + set_instance_parameter_value $axi_regmap {OFFLOAD0_CMD_MEM_ADDRESS_WIDTH} $cmd_mem_addr_width + set_instance_parameter_value $axi_regmap {OFFLOAD0_SDO_MEM_ADDRESS_WIDTH} $data_mem_addr_width + set_instance_parameter_value $axi_regmap {SDI_FIFO_ADDRESS_WIDTH} $sdi_fifo_addr_width + set_instance_parameter_value $axi_regmap {SDO_FIFO_ADDRESS_WIDTH} $sdo_fifo_addr_width + set_instance_parameter_value $axi_regmap {SYNC_FIFO_ADDRESS_WIDTH} $sync_fifo_addr_width + set_instance_parameter_value $axi_regmap {CMD_FIFO_ADDRESS_WIDTH} $cmd_fifo_addr_width + + add_instance $offload spi_engine_offload + set_instance_parameter_value $offload {ASYNC_TRIG} {0} + set_instance_parameter_value $offload {ASYNC_SPI_CLK} 0 + set_instance_parameter_value $offload {DATA_WIDTH} $data_width + set_instance_parameter_value $offload {NUM_OF_SDI} $num_sdi + set_instance_parameter_value $offload {SDO_STREAMING} $sdo_streaming + set_instance_parameter_value $offload {CMD_MEM_ADDRESS_WIDTH} $cmd_mem_addr_width + set_instance_parameter_value $offload {SDO_MEM_ADDRESS_WIDTH} $data_mem_addr_width + + add_instance $interconnect spi_engine_interconnect + set_instance_parameter_value $interconnect {DATA_WIDTH} $data_width + set_instance_parameter_value $interconnect {NUM_OF_SDI} $num_sdi + + # clocks + add_connection $axi_clk $axi_regmap.s_axi_clock + add_connection $spi_clk $axi_regmap.if_spi_clk + add_connection $spi_clk $execution.if_clk + add_connection $spi_clk $interconnect.if_clk + add_connection $spi_clk $offload.if_ctrl_clk + add_connection $spi_clk $offload.if_spi_clk + + # resets + add_connection $axi_reset $axi_regmap.s_axi_reset + add_connection $axi_regmap.if_spi_resetn $execution.if_resetn + add_connection $axi_regmap.if_spi_resetn $interconnect.if_resetn + add_connection $axi_regmap.if_spi_resetn $offload.if_spi_resetn + + # interfaces + add_connection $interconnect.m_cmd $execution.cmd + add_connection $execution.sdi_data $interconnect.m_sdi + add_connection $interconnect.m_sdo $execution.sdo_data + add_connection $execution.sync $interconnect.m_sync + add_connection $axi_regmap.cmd $interconnect.s1_cmd + add_connection $interconnect.s1_sdi $axi_regmap.sdi_data + add_connection $axi_regmap.sdo_data $interconnect.s1_sdo + add_connection $interconnect.s1_sync $axi_regmap.sync + add_connection $offload.cmd $interconnect.s0_cmd + add_connection $interconnect.s0_sdi $offload.sdi_data + add_connection $offload.sdo_data $interconnect.s0_sdo + add_connection $interconnect.s0_sync $offload.sync + add_connection $offload.m_interconnect_ctrl $interconnect.s_interconnect_ctrl + add_connection $offload.ctrl_cmd_wr $axi_regmap.offload0_cmd + add_connection $offload.ctrl_sdo_wr $axi_regmap.offload0_sdo + add_connection $offload.if_ctrl_enable $axi_regmap.if_offload0_enable + add_connection $offload.if_ctrl_enabled $axi_regmap.if_offload0_enabled + add_connection $offload.if_ctrl_mem_reset $axi_regmap.if_offload0_mem_reset + add_connection $offload.status_sync $axi_regmap.offload_sync + +} \ No newline at end of file From 9b630672689d96ca7c5ed837eddca7ca76b086db Mon Sep 17 00:00:00 2001 From: Laez Barbosa Date: Mon, 13 Oct 2025 12:52:17 -0300 Subject: [PATCH 3/6] library/spi_engine: add missing parameter to xilinx script Signed-off-by: Laez Barbosa --- library/spi_engine/scripts/spi_engine_xilinx.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/library/spi_engine/scripts/spi_engine_xilinx.tcl b/library/spi_engine/scripts/spi_engine_xilinx.tcl index d4d7852aa7e..8fde294ef4e 100644 --- a/library/spi_engine/scripts/spi_engine_xilinx.tcl +++ b/library/spi_engine/scripts/spi_engine_xilinx.tcl @@ -53,6 +53,7 @@ proc spi_engine_create {{name "spi_engine"} ad_ip_parameter $execution CONFIG.ECHO_SCLK $echo_sclk ad_ip_instance axi_spi_engine $axi_regmap + ad_ip_parameter $axi_regmap CONFIG.MM_IF_TYPE 0 ad_ip_parameter $axi_regmap CONFIG.DATA_WIDTH $data_width ad_ip_parameter $axi_regmap CONFIG.NUM_OFFLOAD 1 ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDI $num_sdi From 4e0605b2220d578149c65bda5ae3c5c6eb947024 Mon Sep 17 00:00:00 2001 From: Laez Barbosa Date: Mon, 13 Oct 2025 12:55:51 -0300 Subject: [PATCH 4/6] library/spi_engine/spi_engine_execution: add missing parameter to _hw.tcl Signed-off-by: Laez Barbosa --- .../spi_engine_execution/spi_engine_execution_hw.tcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl b/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl index f2d95966097..6efb3180050 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl @@ -20,8 +20,9 @@ ad_ip_parameter DEFAULT_SPI_CFG INTEGER 0 ad_ip_parameter DEFAULT_CLK_DIV INTEGER 0 ad_ip_parameter DATA_WIDTH INTEGER 8 ad_ip_parameter NUM_OF_SDI INTEGER 1 -ad_ip_parameter SDI_DELAY INTEGER 0 ad_ip_parameter SDO_DEFAULT INTEGER 0 +ad_ip_parameter ECHO_SCLK INTEGER 0 +ad_ip_parameter SDI_DELAY INTEGER 0 proc p_elaboration {} { From ea07cc342d40031c3ec2a602f021523d7d6db88e Mon Sep 17 00:00:00 2001 From: Laez Barbosa Date: Fri, 17 Oct 2025 17:11:11 -0300 Subject: [PATCH 5/6] projects: change intel SPI Engine projects to use new script Signed-off-by: Laez Barbosa --- projects/ad4052_ardz/common/ad4052_qsys.tcl | 100 +++++----------- .../common/ad411x_ad717x_asdz_qsys.tcl | 107 +++++------------- .../ad4170_asdz/common/ad4170_asdz_qsys.tcl | 92 ++++----------- projects/ad469x_evb/common/ad469x_qsys.tcl | 100 +++++----------- .../ad57xx_ardz/common/ad57xx_ardz_qsys.tcl | 104 +++++------------ projects/cn0540/common/cn0540_qsys.tcl | 92 ++++----------- projects/cn0561/common/cn0561_qsys.tcl | 101 +++++------------ 7 files changed, 193 insertions(+), 503 deletions(-) diff --git a/projects/ad4052_ardz/common/ad4052_qsys.tcl b/projects/ad4052_ardz/common/ad4052_qsys.tcl index 89e0f8c2c3d..8800d372eca 100644 --- a/projects/ad4052_ardz/common/ad4052_qsys.tcl +++ b/projects/ad4052_ardz/common/ad4052_qsys.tcl @@ -11,36 +11,6 @@ set_instance_parameter_value axi_dmac_0 {CYCLIC} {0} set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32} set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128} -# axi_spi_engine - -add_instance axi_spi_engine_0 axi_spi_engine -set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} -set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} -set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1} -set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} - -# spi_engine_execution - -add_instance spi_engine_execution_0 spi_engine_execution -set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1} -set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} - -# spi_engine_interconnect - -add_instance spi_engine_interconnect_0 spi_engine_interconnect -set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} - -# spi_engine_offload - -add_instance spi_engine_offload_0 spi_engine_offload -set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} -set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} -set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1} - # axi_pwm_gen add_instance pwm_trigger axi_pwm_gen @@ -87,6 +57,26 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig. set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPortLSB {0} set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll width {0} +# spi engine +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_intel.tcl + +set spi_engine_hier spi_ad4052 + +set data_width 32 +set async_spi_clk 1 +set num_cs 1 +set num_sdi 1 +set num_sdo 1 +set sdi_delay 0 +set echo_sclk 0 +set sdo_streaming 0 + +set axi_clk sys_clk.clk +set axi_reset sys_clk.clk_reset +set spi_clk spi_clk_pll.outclk0 + +spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming +set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1} # exported interface add_interface adc_spi_sclk clock source @@ -95,27 +85,21 @@ add_interface adc_spi_sdo conduit end add_interface adc_spi_cs conduit end add_interface adc_drdy conduit end -set_interface_property adc_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk -set_interface_property adc_spi_sdi EXPORT_OF spi_engine_execution_0.if_sdi -set_interface_property adc_spi_sdo EXPORT_OF spi_engine_execution_0.if_sdo -set_interface_property adc_spi_cs EXPORT_OF spi_engine_execution_0.if_cs -set_interface_property adc_drdy_trigger EXPORT_OF spi_engine_offload_0.if_trigger +set_interface_property adc_spi_sclk EXPORT_OF ${spi_engine_hier}_execution.if_sclk +set_interface_property adc_spi_sdi EXPORT_OF ${spi_engine_hier}_execution.if_sdi +set_interface_property adc_spi_sdo EXPORT_OF ${spi_engine_hier}_execution.if_sdo +set_interface_property adc_spi_cs EXPORT_OF ${spi_engine_hier}_execution.if_cs +set_interface_property adc_drdy_trigger EXPORT_OF ${spi_engine_hier}_offload.if_trigger set_interface_property adc_cnv EXPORT_OF pwm_trigger.if_pwm_0 # clocks add_connection sys_clk.clk spi_clk_pll.refclk add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk -add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock add_connection sys_clk.clk axi_dmac_0.s_axi_clock add_connection sys_clk.clk pwm_trigger.s_axi_clock add_connection spi_clk_pll.outclk0 pwm_trigger.if_ext_clk -add_connection spi_clk_pll.outclk0 spi_engine_execution_0.if_clk -add_connection spi_clk_pll.outclk0 spi_engine_interconnect_0.if_clk -add_connection spi_clk_pll.outclk0 axi_spi_engine_0.if_spi_clk -add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_ctrl_clk -add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_spi_clk add_connection spi_clk_pll.outclk0 axi_dmac_0.if_s_axis_aclk add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock @@ -124,47 +108,19 @@ add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock add_connection sys_clk.clk_reset spi_clk_pll.reset add_connection sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset -add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset add_connection sys_clk.clk_reset pwm_trigger.s_axi_reset -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn - add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset # interfaces -add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd -add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi -add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data -add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync - -add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd -add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data -add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo -add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync - -add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd -add_connection spi_engine_interconnect_0.s0_sdi spi_engine_offload_0.sdi_data -add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo -add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync -add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl - -add_connection spi_engine_offload_0.ctrl_cmd_wr axi_spi_engine_0.offload0_cmd -add_connection spi_engine_offload_0.ctrl_sdo_wr axi_spi_engine_0.offload0_sdo -add_connection spi_engine_offload_0.if_ctrl_enable axi_spi_engine_0.if_offload0_enable -add_connection spi_engine_offload_0.if_ctrl_enabled axi_spi_engine_0.if_offload0_enabled -add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset -add_connection spi_engine_offload_0.status_sync axi_spi_engine_0.offload_sync - -add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis +add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis # cpu interconnects ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi -ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi +ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi ad_cpu_interconnect 0x00040000 pwm_trigger.s_axi ad_cpu_interconnect 0x00050000 spi_clk_pll_reconfig.mgmt_avalon_slave @@ -175,4 +131,4 @@ ad_dma_interconnect axi_dmac_0.m_dest_axi #interrupts ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender -ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender +ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender diff --git a/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl b/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl index 2dea096fd42..91ea8dbf6e5 100644 --- a/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl +++ b/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl @@ -12,40 +12,31 @@ set_instance_parameter_value axi_dmac_0 {CYCLIC} {0} set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32} set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128} -# axi_spi_engine - -add_instance axi_spi_engine_0 axi_spi_engine -set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} -set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} -set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1} -set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} - -# spi_engine_execution +# util_sigma_delta_spi -add_instance spi_engine_execution_0 spi_engine_execution -set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1} -set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} +add_instance util_sigma_delta_spi util_sigma_delta_spi +set_instance_parameter_value util_sigma_delta_spi {NUM_OF_CS} {1} -# spi_engine_interconnect +# spi engine +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_intel.tcl -add_instance spi_engine_interconnect_0 spi_engine_interconnect -set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} +set spi_engine_hier spi_ad411x_ad717x -# spi_engine_offload +set data_width 32 +set async_spi_clk 1 +set num_cs 1 +set num_sdi 1 +set num_sdo 1 +set sdi_delay 0 +set echo_sclk 0 +set sdo_streaming 0 -add_instance spi_engine_offload_0 spi_engine_offload -set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} -set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} -set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1} +set axi_clk sys_clk.clk +set axi_reset sys_clk.clk_reset +set spi_clk sys_dma_clk.clk -# util_sigma_delta_spi - -add_instance util_sigma_delta_spi util_sigma_delta_spi -set_instance_parameter_value util_sigma_delta_spi {NUM_OF_CS} {1} +spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming +set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1} # exported interface @@ -64,73 +55,37 @@ set_interface_property ad411x_spi_trigger EXPORT_OF util_sigma_delta_spi.if_data # clocks -add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock add_connection sys_clk.clk axi_dmac_0.s_axi_clock +add_connection sys_dma_clk.clk axi_dmac_0.if_s_axis_aclk +add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock + # util_sigma_delta_connection add_connection sys_dma_clk.clk util_sigma_delta_spi.if_clk add_connection sys_clk.clk_reset util_sigma_delta_spi.if_resetn -add_connection spi_engine_execution_0.if_cs util_sigma_delta_spi.if_s_cs -add_connection spi_engine_execution_0.if_sclk util_sigma_delta_spi.if_s_sclk -add_connection spi_engine_execution_0.if_sdi util_sigma_delta_spi.if_s_sdi -add_connection spi_engine_execution_0.if_sdo util_sigma_delta_spi.if_s_sdo -add_connection spi_engine_execution_0.if_sdo_t util_sigma_delta_spi.if_s_sdo_t -add_connection spi_engine_offload_0.if_trigger util_sigma_delta_spi.if_data_ready - -# add_connection axi_spi_engine_0. - -add_connection sys_dma_clk.clk spi_engine_execution_0.if_clk -add_connection sys_dma_clk.clk spi_engine_interconnect_0.if_clk -add_connection sys_dma_clk.clk axi_spi_engine_0.if_spi_clk -add_connection sys_dma_clk.clk spi_engine_offload_0.if_ctrl_clk -add_connection sys_dma_clk.clk spi_engine_offload_0.if_spi_clk -add_connection sys_dma_clk.clk axi_dmac_0.if_s_axis_aclk -add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock +add_connection ${spi_engine_hier}_execution.if_cs util_sigma_delta_spi.if_s_cs +add_connection ${spi_engine_hier}_execution.if_sclk util_sigma_delta_spi.if_s_sclk +add_connection ${spi_engine_hier}_execution.if_sdi util_sigma_delta_spi.if_s_sdi +add_connection ${spi_engine_hier}_execution.if_sdo util_sigma_delta_spi.if_s_sdo +add_connection ${spi_engine_hier}_execution.if_sdo_t util_sigma_delta_spi.if_s_sdo_t +add_connection ${spi_engine_hier}_offload.if_trigger util_sigma_delta_spi.if_data_ready # resets -add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn - add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset # interfaces -add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd -add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi -add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data -add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync - -add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd -add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data -add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo -add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync -add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl - -add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd -add_connection spi_engine_interconnect_0.s0_sdi spi_engine_offload_0.sdi_data -add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo -add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync - -add_connection spi_engine_offload_0.ctrl_cmd_wr axi_spi_engine_0.offload0_cmd -add_connection spi_engine_offload_0.ctrl_sdo_wr axi_spi_engine_0.offload0_sdo -add_connection spi_engine_offload_0.if_ctrl_enable axi_spi_engine_0.if_offload0_enable -add_connection spi_engine_offload_0.if_ctrl_enabled axi_spi_engine_0.if_offload0_enabled -add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset -add_connection spi_engine_offload_0.status_sync axi_spi_engine_0.offload_sync - -add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis +add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis # cpu interconnects ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi -ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi +ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi # dma interconnect ad_dma_interconnect axi_dmac_0.m_dest_axi @@ -138,4 +93,4 @@ ad_dma_interconnect axi_dmac_0.m_dest_axi # interrupts ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender -ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender +ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender diff --git a/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl b/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl index 666404987a2..a69b6abb955 100644 --- a/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl +++ b/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl @@ -13,35 +13,26 @@ set_instance_parameter_value axi_dmac_0 {CYCLIC} {0} set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32} set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {64} -# axi_spi_engine +# spi engine +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_intel.tcl -add_instance axi_spi_engine_0 axi_spi_engine -set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} -set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} -set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1} -set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} +set spi_engine_hier spi_ad4170 -# spi_engine_execution +set data_width 32 +set async_spi_clk 1 +set num_cs 1 +set num_sdi 1 +set num_sdo 1 +set sdi_delay 0 +set echo_sclk 0 +set sdo_streaming 0 -add_instance spi_engine_execution_0 spi_engine_execution -set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1} -set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} +set axi_clk sys_clk.clk +set axi_reset sys_clk.clk_reset +set spi_clk sys_dma_clk.clk -# spi_engine_interconnect - -add_instance spi_engine_interconnect_0 spi_engine_interconnect -set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} - -# spi_engine_offload - -add_instance spi_engine_offload_0 spi_engine_offload -set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} -set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} -set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1} +spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming +set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1} # exported interface @@ -51,67 +42,32 @@ add_interface ad4170_spi_sdi conduit end add_interface ad4170_spi_sdo conduit end add_interface ad4170_spi_trigger conduit end -set_interface_property ad4170_spi_cs EXPORT_OF spi_engine_execution_0.if_cs -set_interface_property ad4170_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk -set_interface_property ad4170_spi_sdi EXPORT_OF spi_engine_execution_0.if_sdi -set_interface_property ad4170_spi_sdo EXPORT_OF spi_engine_execution_0.if_sdo -set_interface_property ad4170_spi_trigger EXPORT_OF spi_engine_offload_0.if_trigger +set_interface_property ad4170_spi_cs EXPORT_OF ${spi_engine_hier}_execution.if_cs +set_interface_property ad4170_spi_sclk EXPORT_OF ${spi_engine_hier}_execution.if_sclk +set_interface_property ad4170_spi_sdi EXPORT_OF ${spi_engine_hier}_execution.if_sdi +set_interface_property ad4170_spi_sdo EXPORT_OF ${spi_engine_hier}_execution.if_sdo +set_interface_property ad4170_spi_trigger EXPORT_OF ${spi_engine_hier}_offload.if_trigger # clocks -add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock add_connection sys_clk.clk axi_dmac_0.s_axi_clock -add_connection sys_dma_clk.clk spi_engine_execution_0.if_clk -add_connection sys_dma_clk.clk spi_engine_interconnect_0.if_clk -add_connection sys_dma_clk.clk axi_spi_engine_0.if_spi_clk -add_connection sys_dma_clk.clk spi_engine_offload_0.if_ctrl_clk -add_connection sys_dma_clk.clk spi_engine_offload_0.if_spi_clk add_connection sys_dma_clk.clk axi_dmac_0.if_s_axis_aclk add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock # resets -add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn - add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset # interfaces - -add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd -add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi -add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data -add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync - -add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd -add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data -add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo -add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync - -add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd -add_connection spi_engine_interconnect_0.s0_sdi spi_engine_offload_0.sdi_data -add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo -add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync -add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl - -add_connection spi_engine_offload_0.ctrl_cmd_wr axi_spi_engine_0.offload0_cmd -add_connection spi_engine_offload_0.ctrl_sdo_wr axi_spi_engine_0.offload0_sdo -add_connection spi_engine_offload_0.if_ctrl_enable axi_spi_engine_0.if_offload0_enable -add_connection spi_engine_offload_0.if_ctrl_enabled axi_spi_engine_0.if_offload0_enabled -add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset -add_connection spi_engine_offload_0.status_sync axi_spi_engine_0.offload_sync - -add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis +add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis # cpu interconnects ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi -ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi +ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi # dma interconnect ad_dma_interconnect axi_dmac_0.m_dest_axi @@ -119,4 +75,4 @@ ad_dma_interconnect axi_dmac_0.m_dest_axi #interrupts ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender -ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender +ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender diff --git a/projects/ad469x_evb/common/ad469x_qsys.tcl b/projects/ad469x_evb/common/ad469x_qsys.tcl index 1d70a7c328c..4d82480a95d 100644 --- a/projects/ad469x_evb/common/ad469x_qsys.tcl +++ b/projects/ad469x_evb/common/ad469x_qsys.tcl @@ -13,36 +13,6 @@ set_instance_parameter_value axi_dmac_0 {CYCLIC} {0} set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32} set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {64} -# axi_spi_engine - -add_instance axi_spi_engine_0 axi_spi_engine -set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} -set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} -set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1} -set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} - -# spi_engine_execution - -add_instance spi_engine_execution_0 spi_engine_execution -set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1} -set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} - -# spi_engine_interconnect - -add_instance spi_engine_interconnect_0 spi_engine_interconnect -set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} - -# spi_engine_offload - -add_instance spi_engine_offload_0 spi_engine_offload -set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} -set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} -set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1} - # axi pwm gen add_instance ad469x_trigger_gen axi_pwm_gen @@ -90,6 +60,26 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig. set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPortLSB {0} set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll width {0} +# spi engine +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_intel.tcl + +set spi_engine_hier ad469x_spi + +set data_width 32 +set async_spi_clk 1 +set num_cs 1 +set num_sdi 1 +set num_sdo 1 +set sdi_delay 0 +set echo_sclk 0 +set sdo_streaming 0 + +set axi_clk sys_clk.clk +set axi_reset sys_clk.clk_reset +set spi_clk spi_clk_pll.outclk0 + +spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming +set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1} # exported interface @@ -100,11 +90,11 @@ add_interface ad469x_spi_sdo conduit end add_interface ad469x_spi_trigger conduit end add_interface ad469x_spi_cnv conduit end -set_interface_property ad469x_spi_cs EXPORT_OF spi_engine_execution_0.if_cs -set_interface_property ad469x_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk -set_interface_property ad469x_spi_sdi EXPORT_OF spi_engine_execution_0.if_sdi -set_interface_property ad469x_spi_sdo EXPORT_OF spi_engine_execution_0.if_sdo -set_interface_property ad469x_spi_trigger EXPORT_OF spi_engine_offload_0.if_trigger +set_interface_property ad469x_spi_cs EXPORT_OF ${spi_engine_hier}_execution.if_cs +set_interface_property ad469x_spi_sclk EXPORT_OF ${spi_engine_hier}_execution.if_sclk +set_interface_property ad469x_spi_sdi EXPORT_OF ${spi_engine_hier}_execution.if_sdi +set_interface_property ad469x_spi_sdo EXPORT_OF ${spi_engine_hier}_execution.if_sdo +set_interface_property ad469x_spi_trigger EXPORT_OF ${spi_engine_hier}_offload.if_trigger set_interface_property ad469x_spi_cnv EXPORT_OF ad469x_trigger_gen.if_pwm_0 # clocks @@ -112,15 +102,9 @@ set_interface_property ad469x_spi_cnv EXPORT_OF ad469x_trigger_gen.if_pwm_0 add_connection sys_clk.clk spi_clk_pll.refclk add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk add_connection sys_clk.clk ad469x_trigger_gen.s_axi_clock -add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock add_connection sys_clk.clk axi_dmac_0.s_axi_clock add_connection spi_clk_pll.outclk0 ad469x_trigger_gen.if_ext_clk -add_connection spi_clk_pll.outclk0 spi_engine_execution_0.if_clk -add_connection spi_clk_pll.outclk0 spi_engine_interconnect_0.if_clk -add_connection spi_clk_pll.outclk0 axi_spi_engine_0.if_spi_clk -add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_ctrl_clk -add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_spi_clk add_connection spi_clk_pll.outclk0 axi_dmac_0.if_s_axis_aclk add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock @@ -129,42 +113,14 @@ add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock add_connection sys_clk.clk_reset spi_clk_pll.reset add_connection sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset -add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset add_connection sys_clk.clk_reset ad469x_trigger_gen.s_axi_reset -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn - add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset # interfaces -add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd -add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi -add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data -add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync - -add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd -add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data -add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo -add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync - -add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd -add_connection spi_engine_interconnect_0.s0_sdi spi_engine_offload_0.sdi_data -add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo -add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync -add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl - -add_connection spi_engine_offload_0.ctrl_cmd_wr axi_spi_engine_0.offload0_cmd -add_connection spi_engine_offload_0.ctrl_sdo_wr axi_spi_engine_0.offload0_sdo -add_connection spi_engine_offload_0.if_ctrl_enable axi_spi_engine_0.if_offload0_enable -add_connection spi_engine_offload_0.if_ctrl_enabled axi_spi_engine_0.if_offload0_enabled -add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset -add_connection spi_engine_offload_0.status_sync axi_spi_engine_0.offload_sync - -add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis +add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis add_interface dma_xfer_req conduit end @@ -173,7 +129,7 @@ set_interface_property dma_xfer_req EXPORT_OF axi_dmac_0.if_s_axis_xfer_req # cpu interconnects ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi -ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi +ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi ad_cpu_interconnect 0x00040000 ad469x_trigger_gen.s_axi # dma interconnect @@ -183,4 +139,4 @@ ad_dma_interconnect axi_dmac_0.m_dest_axi #interrupts ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender -ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender +ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender \ No newline at end of file diff --git a/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl b/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl index 170d5c9e0a1..02738020c9e 100644 --- a/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl +++ b/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl @@ -12,37 +12,6 @@ set_instance_parameter_value ad57xx_dma {CYCLIC} {0} set_instance_parameter_value ad57xx_dma {DMA_DATA_WIDTH_SRC} {128} set_instance_parameter_value ad57xx_dma {DMA_DATA_WIDTH_DEST} {32} -# axi_spi_engine - -add_instance axi_spi_engine_0 axi_spi_engine -set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} -set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} -set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1} -set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} - -# spi_engine_execution - -add_instance spi_engine_execution_0 spi_engine_execution -set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1} -set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} - -# spi_engine_interconnect - -add_instance spi_engine_interconnect_0 spi_engine_interconnect -set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} - -# spi_engine_offload - -add_instance spi_engine_offload_0 spi_engine_offload -set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} -set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} -set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1} -set_instance_parameter_value spi_engine_offload_0 {SDO_STREAMING} {1} - # axi pwm gen add_instance trig_gen axi_pwm_gen @@ -90,6 +59,26 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig. set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPortLSB {0} set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll width {0} +# spi engine +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_intel.tcl + +set spi_engine_hier spi_ad57xx + +set data_width 32 +set async_spi_clk 1 +set num_cs 1 +set num_sdi 1 +set num_sdo 1 +set sdi_delay 0 +set echo_sclk 0 +set sdo_streaming 1 + +set axi_clk sys_clk.clk +set axi_reset sys_clk.clk_reset +set spi_clk spi_clk_pll.outclk0 + +spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming + # exported interface add_interface ad57xx_spi_sclk clock source @@ -98,27 +87,21 @@ add_interface ad57xx_spi_miso conduit end add_interface ad57xx_spi_mosi conduit end add_interface m_axis_offload_sdi axi4stream end -set_interface_property ad57xx_spi_cs EXPORT_OF spi_engine_execution_0.if_cs -set_interface_property ad57xx_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk -set_interface_property ad57xx_spi_miso EXPORT_OF spi_engine_execution_0.if_sdi -set_interface_property ad57xx_spi_mosi EXPORT_OF spi_engine_execution_0.if_sdo -set_interface_property m_axis_offload_sdi EXPORT_OF spi_engine_offload_0.offload_sdi +set_interface_property ad57xx_spi_cs EXPORT_OF ${spi_engine_hier}_execution.if_cs +set_interface_property ad57xx_spi_sclk EXPORT_OF ${spi_engine_hier}_execution.if_sclk +set_interface_property ad57xx_spi_miso EXPORT_OF ${spi_engine_hier}_execution.if_sdi +set_interface_property ad57xx_spi_mosi EXPORT_OF ${spi_engine_hier}_execution.if_sdo +set_interface_property m_axis_offload_sdi EXPORT_OF ${spi_engine_hier}_offload.offload_sdi # clocks add_connection sys_clk.clk spi_clk_pll.refclk add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk -add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock add_connection sys_clk.clk ad57xx_dma.s_axi_clock add_connection sys_clk.clk trig_gen.s_axi_clock add_connection spi_clk_pll.outclk0 trig_gen.if_ext_clk -add_connection spi_clk_pll.outclk0 spi_engine_execution_0.if_clk -add_connection spi_clk_pll.outclk0 spi_engine_interconnect_0.if_clk -add_connection spi_clk_pll.outclk0 axi_spi_engine_0.if_spi_clk -add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_ctrl_clk -add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_spi_clk add_connection spi_clk_pll.outclk0 ad57xx_dma.if_m_axis_aclk add_connection sys_dma_clk.clk ad57xx_dma.m_src_axi_clock @@ -126,48 +109,19 @@ add_connection sys_dma_clk.clk ad57xx_dma.m_src_axi_clock add_connection sys_clk.clk_reset spi_clk_pll.reset add_connection sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset -add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset add_connection sys_clk.clk_reset ad57xx_dma.s_axi_reset add_connection sys_clk.clk_reset trig_gen.s_axi_reset -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn - add_connection sys_dma_clk.clk_reset ad57xx_dma.m_src_axi_reset # interfaces - -add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd -add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi -add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data -add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync - -add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd -add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data -add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo -add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync - -add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd -add_connection spi_engine_interconnect_0.s0_sdi spi_engine_offload_0.sdi_data -add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo -add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync -add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl - -add_connection spi_engine_offload_0.ctrl_cmd_wr axi_spi_engine_0.offload0_cmd -add_connection spi_engine_offload_0.ctrl_sdo_wr axi_spi_engine_0.offload0_sdo -add_connection spi_engine_offload_0.if_ctrl_enable axi_spi_engine_0.if_offload0_enable -add_connection spi_engine_offload_0.if_ctrl_enabled axi_spi_engine_0.if_offload0_enabled -add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset -add_connection spi_engine_offload_0.status_sync axi_spi_engine_0.offload_sync -add_connection spi_engine_offload_0.if_trigger trig_gen.if_pwm_0 - -add_connection ad57xx_dma.m_axis spi_engine_offload_0.s_axis_sdo +add_connection ${spi_engine_hier}_offload.if_trigger trig_gen.if_pwm_0 +add_connection ad57xx_dma.m_axis ${spi_engine_hier}_offload.s_axis_sdo # cpu interconnects ad_cpu_interconnect 0x00030000 ad57xx_dma.s_axi -ad_cpu_interconnect 0x00040000 axi_spi_engine_0.s_axi +ad_cpu_interconnect 0x00040000 ${spi_engine_hier}_axi_regmap.s_axi ad_cpu_interconnect 0x00050000 trig_gen.s_axi ad_cpu_interconnect 0x00060000 spi_clk_pll_reconfig.mgmt_avalon_slave @@ -178,4 +132,4 @@ ad_dma_interconnect ad57xx_dma.m_src_axi #interrupts ad_cpu_interrupt 4 ad57xx_dma.interrupt_sender -ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender +ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender diff --git a/projects/cn0540/common/cn0540_qsys.tcl b/projects/cn0540/common/cn0540_qsys.tcl index 1eec853d626..11215668f0d 100755 --- a/projects/cn0540/common/cn0540_qsys.tcl +++ b/projects/cn0540/common/cn0540_qsys.tcl @@ -12,35 +12,26 @@ set_instance_parameter_value axi_dmac_0 {CYCLIC} {0} set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32} set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128} -# axi_spi_engine +# spi engine +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_intel.tcl -add_instance axi_spi_engine_0 axi_spi_engine -set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} -set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} -set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1} -set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} +set spi_engine_hier cn0540_spi -# spi_engine_execution +set data_width 32 +set async_spi_clk 1 +set num_cs 1 +set num_sdi 1 +set num_sdo 1 +set sdi_delay 0 +set echo_sclk 0 +set sdo_streaming 0 -add_instance spi_engine_execution_0 spi_engine_execution -set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1} -set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} +set axi_clk sys_clk.clk +set axi_reset sys_clk.clk_reset +set spi_clk sys_dma_clk.clk -# spi_engine_interconnect - -add_instance spi_engine_interconnect_0 spi_engine_interconnect -set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} - -# spi_engine_offload - -add_instance spi_engine_offload_0 spi_engine_offload -set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} -set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} -set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1} +spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming +set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1} # exported interface @@ -50,67 +41,33 @@ add_interface cn0540_spi_sdi conduit end add_interface cn0540_spi_sdo conduit end add_interface cn0540_spi_trigger conduit end -set_interface_property cn0540_spi_cs EXPORT_OF spi_engine_execution_0.if_cs -set_interface_property cn0540_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk -set_interface_property cn0540_spi_sdi EXPORT_OF spi_engine_execution_0.if_sdi -set_interface_property cn0540_spi_sdo EXPORT_OF spi_engine_execution_0.if_sdo -set_interface_property cn0540_spi_trigger EXPORT_OF spi_engine_offload_0.if_trigger +set_interface_property cn0540_spi_cs EXPORT_OF ${spi_engine_hier}_execution.if_cs +set_interface_property cn0540_spi_sclk EXPORT_OF ${spi_engine_hier}_execution.if_sclk +set_interface_property cn0540_spi_sdi EXPORT_OF ${spi_engine_hier}_execution.if_sdi +set_interface_property cn0540_spi_sdo EXPORT_OF ${spi_engine_hier}_execution.if_sdo +set_interface_property cn0540_spi_trigger EXPORT_OF ${spi_engine_hier}_offload.if_trigger # clocks -add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock add_connection sys_clk.clk axi_dmac_0.s_axi_clock -add_connection sys_dma_clk.clk spi_engine_execution_0.if_clk -add_connection sys_dma_clk.clk spi_engine_interconnect_0.if_clk -add_connection sys_dma_clk.clk axi_spi_engine_0.if_spi_clk -add_connection sys_dma_clk.clk spi_engine_offload_0.if_ctrl_clk -add_connection sys_dma_clk.clk spi_engine_offload_0.if_spi_clk add_connection sys_dma_clk.clk axi_dmac_0.if_s_axis_aclk add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock # resets -add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn - add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset # interfaces -add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd -add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi -add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data -add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync - -add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd -add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data -add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo -add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync - -add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd -add_connection spi_engine_interconnect_0.s0_sdi spi_engine_offload_0.sdi_data -add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo -add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync -add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl - -add_connection spi_engine_offload_0.ctrl_cmd_wr axi_spi_engine_0.offload0_cmd -add_connection spi_engine_offload_0.ctrl_sdo_wr axi_spi_engine_0.offload0_sdo -add_connection spi_engine_offload_0.if_ctrl_enable axi_spi_engine_0.if_offload0_enable -add_connection spi_engine_offload_0.if_ctrl_enabled axi_spi_engine_0.if_offload0_enabled -add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset -add_connection spi_engine_offload_0.status_sync axi_spi_engine_0.offload_sync - -add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis +add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis # cpu interconnects ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi -ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi +ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi # dma interconnect ad_dma_interconnect axi_dmac_0.m_dest_axi @@ -118,5 +75,4 @@ ad_dma_interconnect axi_dmac_0.m_dest_axi #interrupts ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender -ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender - +ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender diff --git a/projects/cn0561/common/cn0561_qsys.tcl b/projects/cn0561/common/cn0561_qsys.tcl index 7e245f9d810..13c5076783f 100644 --- a/projects/cn0561/common/cn0561_qsys.tcl +++ b/projects/cn0561/common/cn0561_qsys.tcl @@ -11,36 +11,6 @@ set_instance_parameter_value axi_dmac_0 {CYCLIC} {0} set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {128} set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128} -# axi_spi_engine - -add_instance axi_spi_engine_0 axi_spi_engine -set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} -set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} -set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {4} -set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} - -# spi_engine_execution - -add_instance spi_engine_execution_0 spi_engine_execution -set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {4} -set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} - -# spi_engine_interconnect - -add_instance spi_engine_interconnect_0 spi_engine_interconnect -set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {4} - -# spi_engine_offload - -add_instance spi_engine_offload_0 spi_engine_offload -set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} -set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} -set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {4} - # axi pwm gen add_instance odr_generator axi_pwm_gen @@ -91,6 +61,27 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig. set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPortLSB {0} set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll width {0} +# spi engine +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_intel.tcl + +set spi_engine_hier cn0561_spi + +set data_width 32 +set async_spi_clk 1 +set num_cs 1 +set num_sdi 4 +set num_sdo 1 +set sdi_delay 0 +set echo_sclk 0 +set sdo_streaming 0 + +set axi_clk sys_clk.clk +set axi_reset sys_clk.clk_reset +set spi_clk spi_clk_pll.outclk0 + +spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming +set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1} + # exported interface add_interface cn0561_spi_sclk clock source @@ -99,26 +90,20 @@ add_interface cn0561_spi_sdi conduit end add_interface cn0561_spi_sdo conduit end add_interface ad4134_odr conduit end -set_interface_property cn0561_spi_cs EXPORT_OF spi_engine_execution_0.if_cs -set_interface_property cn0561_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk -set_interface_property cn0561_spi_sdi EXPORT_OF spi_engine_execution_0.if_sdi -set_interface_property cn0561_spi_sdo EXPORT_OF spi_engine_execution_0.if_sdo +set_interface_property cn0561_spi_cs EXPORT_OF ${spi_engine_hier}_execution.if_cs +set_interface_property cn0561_spi_sclk EXPORT_OF ${spi_engine_hier}_execution.if_sclk +set_interface_property cn0561_spi_sdi EXPORT_OF ${spi_engine_hier}_execution.if_sdi +set_interface_property cn0561_spi_sdo EXPORT_OF ${spi_engine_hier}_execution.if_sdo set_interface_property ad4134_odr EXPORT_OF odr_generator.if_pwm_1 # clocks add_connection sys_clk.clk spi_clk_pll.refclk add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk -add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock add_connection sys_clk.clk axi_dmac_0.s_axi_clock add_connection sys_clk.clk odr_generator.s_axi_clock add_connection spi_clk_pll.outclk0 odr_generator.if_ext_clk -add_connection spi_clk_pll.outclk0 spi_engine_execution_0.if_clk -add_connection spi_clk_pll.outclk0 spi_engine_interconnect_0.if_clk -add_connection spi_clk_pll.outclk0 axi_spi_engine_0.if_spi_clk -add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_ctrl_clk -add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_spi_clk add_connection spi_clk_pll.outclk0 axi_dmac_0.if_s_axis_aclk add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock @@ -127,48 +112,20 @@ add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock add_connection sys_clk.clk_reset spi_clk_pll.reset add_connection sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset -add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset add_connection sys_clk.clk_reset odr_generator.s_axi_reset -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn -add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn - add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset # interfaces -add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd -add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi -add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data -add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync - -add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd -add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data -add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo -add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync - -add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd -add_connection spi_engine_interconnect_0.s0_sdi spi_engine_offload_0.sdi_data -add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo -add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync -add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl - -add_connection spi_engine_offload_0.ctrl_cmd_wr axi_spi_engine_0.offload0_cmd -add_connection spi_engine_offload_0.ctrl_sdo_wr axi_spi_engine_0.offload0_sdo -add_connection spi_engine_offload_0.if_ctrl_enable axi_spi_engine_0.if_offload0_enable -add_connection spi_engine_offload_0.if_ctrl_enabled axi_spi_engine_0.if_offload0_enabled -add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset -add_connection spi_engine_offload_0.status_sync axi_spi_engine_0.offload_sync - -add_connection spi_engine_offload_0.if_trigger odr_generator.if_pwm_0 -add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis +add_connection ${spi_engine_hier}_offload.if_trigger odr_generator.if_pwm_0 +add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis # cpu interconnects ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi -ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi +ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi ad_cpu_interconnect 0x00040000 odr_generator.s_axi # dma interconnect @@ -178,4 +135,4 @@ ad_dma_interconnect axi_dmac_0.m_dest_axi #interrupts ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender -ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender +ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender \ No newline at end of file From 09cac9cac86f9ccb5e70999c2f309c44357c6668 Mon Sep 17 00:00:00 2001 From: Laez Barbosa Date: Thu, 23 Oct 2025 17:45:37 -0300 Subject: [PATCH 6/6] update headers Signed-off-by: Laez Barbosa --- projects/ad4052_ardz/common/ad4052_bd.tcl | 2 +- projects/ad4052_ardz/coraz7s/Makefile | 2 +- projects/ad4134_fmc/common/ad4134_bd.tcl | 2 +- projects/ad4170_asdz/common/ad4170_asdz_bd.tcl | 2 +- projects/ad4170_asdz/coraz7s/Makefile | 2 +- projects/ad4630_fmc/zed/Makefile | 2 +- projects/ad469x_evb/coraz7s/Makefile | 2 +- projects/ad469x_evb/zed/Makefile | 2 +- projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl | 2 +- projects/ad57xx_ardz/coraz7s/Makefile | 2 +- projects/ad7134_fmc/common/ad7134_bd.tcl | 2 +- projects/ad7134_fmc/zed/Makefile | 2 +- projects/ad738x_fmc/zed/Makefile | 2 +- projects/ad7606x_fmc/common/ad7606x_bd.tcl | 2 +- projects/ad7606x_fmc/zed/Makefile | 2 +- projects/ad77681evb/common/ad77681evb_bd.tcl | 2 +- projects/ad77681evb/zed/Makefile | 2 +- projects/adaq7980_sdz/common/adaq7980_bd.tcl | 2 +- projects/adaq7980_sdz/zed/Makefile | 2 +- projects/cn0363/zed/Makefile | 2 +- projects/cn0540/common/cn0540_bd.tcl | 2 +- projects/cn0540/coraz7s/Makefile | 2 +- projects/cn0561/common/cn0561_bd.tcl | 2 +- projects/cn0561/coraz7s/Makefile | 2 +- projects/cn0561/zed/Makefile | 2 +- projects/pulsar_adc/common/pulsar_adc_bd.tcl | 2 +- 26 files changed, 26 insertions(+), 26 deletions(-) diff --git a/projects/ad4052_ardz/common/ad4052_bd.tcl b/projects/ad4052_ardz/common/ad4052_bd.tcl index 24903ac5547..a7bbd1e3899 100644 --- a/projects/ad4052_ardz/common/ad4052_bd.tcl +++ b/projects/ad4052_ardz/common/ad4052_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/ad4052_ardz/coraz7s/Makefile b/projects/ad4052_ardz/coraz7s/Makefile index f65a0c44d29..bb4d4ce0df9 100644 --- a/projects/ad4052_ardz/coraz7s/Makefile +++ b/projects/ad4052_ardz/coraz7s/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2024 Analog Devices, Inc. +## Copyright (c) 2018 - 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/ad4134_fmc/common/ad4134_bd.tcl b/projects/ad4134_fmc/common/ad4134_bd.tcl index f2deff81d47..39447f168bc 100644 --- a/projects/ad4134_fmc/common/ad4134_bd.tcl +++ b/projects/ad4134_fmc/common/ad4134_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl b/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl index 619b79d17b9..55474260975 100644 --- a/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl +++ b/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/ad4170_asdz/coraz7s/Makefile b/projects/ad4170_asdz/coraz7s/Makefile index c2691112f8b..61b93a18d55 100644 --- a/projects/ad4170_asdz/coraz7s/Makefile +++ b/projects/ad4170_asdz/coraz7s/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2024 Analog Devices, Inc. +## Copyright (c) 2018 - 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/ad4630_fmc/zed/Makefile b/projects/ad4630_fmc/zed/Makefile index 991d5161f03..0935b2517cb 100644 --- a/projects/ad4630_fmc/zed/Makefile +++ b/projects/ad4630_fmc/zed/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2023, 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/ad469x_evb/coraz7s/Makefile b/projects/ad469x_evb/coraz7s/Makefile index 6ae19e870c1..af9401c09bf 100644 --- a/projects/ad469x_evb/coraz7s/Makefile +++ b/projects/ad469x_evb/coraz7s/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2024 Analog Devices, Inc. +## Copyright (c) 2018 - 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/ad469x_evb/zed/Makefile b/projects/ad469x_evb/zed/Makefile index fddda268192..dd3935eeb67 100644 --- a/projects/ad469x_evb/zed/Makefile +++ b/projects/ad469x_evb/zed/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2023, 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl b/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl index 2055e9bd180..8279e7df794 100644 --- a/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl +++ b/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/ad57xx_ardz/coraz7s/Makefile b/projects/ad57xx_ardz/coraz7s/Makefile index 4c2ea7e2850..27c4fe9e4e0 100644 --- a/projects/ad57xx_ardz/coraz7s/Makefile +++ b/projects/ad57xx_ardz/coraz7s/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2024 Analog Devices, Inc. +## Copyright (c) 2018 - 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/ad7134_fmc/common/ad7134_bd.tcl b/projects/ad7134_fmc/common/ad7134_bd.tcl index 2c02bafc7ee..3d08d564b65 100644 --- a/projects/ad7134_fmc/common/ad7134_bd.tcl +++ b/projects/ad7134_fmc/common/ad7134_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/ad7134_fmc/zed/Makefile b/projects/ad7134_fmc/zed/Makefile index 1dad988a4d1..17c15aa8a35 100644 --- a/projects/ad7134_fmc/zed/Makefile +++ b/projects/ad7134_fmc/zed/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2023, 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/ad738x_fmc/zed/Makefile b/projects/ad738x_fmc/zed/Makefile index aa9093a9c1c..4022cf45f61 100644 --- a/projects/ad738x_fmc/zed/Makefile +++ b/projects/ad738x_fmc/zed/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2024 Analog Devices, Inc. +## Copyright (c) 2018 - 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/ad7606x_fmc/common/ad7606x_bd.tcl b/projects/ad7606x_fmc/common/ad7606x_bd.tcl index 5c17ae68ca4..45ffe628631 100644 --- a/projects/ad7606x_fmc/common/ad7606x_bd.tcl +++ b/projects/ad7606x_fmc/common/ad7606x_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/ad7606x_fmc/zed/Makefile b/projects/ad7606x_fmc/zed/Makefile index 1ddd84b7792..1b9b28f5116 100644 --- a/projects/ad7606x_fmc/zed/Makefile +++ b/projects/ad7606x_fmc/zed/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2024 Analog Devices, Inc. +## Copyright (c) 2018 - 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/ad77681evb/common/ad77681evb_bd.tcl b/projects/ad77681evb/common/ad77681evb_bd.tcl index 4c39701d710..dd293472545 100644 --- a/projects/ad77681evb/common/ad77681evb_bd.tcl +++ b/projects/ad77681evb/common/ad77681evb_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/ad77681evb/zed/Makefile b/projects/ad77681evb/zed/Makefile index acf4b3d1bb0..bbcd4692b03 100644 --- a/projects/ad77681evb/zed/Makefile +++ b/projects/ad77681evb/zed/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2024 Analog Devices, Inc. +## Copyright (c) 2018 - 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/adaq7980_sdz/common/adaq7980_bd.tcl b/projects/adaq7980_sdz/common/adaq7980_bd.tcl index 9dae03009ed..654e5f3a204 100644 --- a/projects/adaq7980_sdz/common/adaq7980_bd.tcl +++ b/projects/adaq7980_sdz/common/adaq7980_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/adaq7980_sdz/zed/Makefile b/projects/adaq7980_sdz/zed/Makefile index d013da5ffd4..30896ae5e09 100644 --- a/projects/adaq7980_sdz/zed/Makefile +++ b/projects/adaq7980_sdz/zed/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2023, 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/cn0363/zed/Makefile b/projects/cn0363/zed/Makefile index 2d9719044d9..5fd523334b4 100644 --- a/projects/cn0363/zed/Makefile +++ b/projects/cn0363/zed/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2023, 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/cn0540/common/cn0540_bd.tcl b/projects/cn0540/common/cn0540_bd.tcl index db8d5ce1510..a2eaad7c8b4 100755 --- a/projects/cn0540/common/cn0540_bd.tcl +++ b/projects/cn0540/common/cn0540_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/cn0540/coraz7s/Makefile b/projects/cn0540/coraz7s/Makefile index e66bb98d76c..fb7b51a63df 100755 --- a/projects/cn0540/coraz7s/Makefile +++ b/projects/cn0540/coraz7s/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2024 Analog Devices, Inc. +## Copyright (c) 2018 - 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/cn0561/common/cn0561_bd.tcl b/projects/cn0561/common/cn0561_bd.tcl index 78d043b6201..7f2f058911e 100644 --- a/projects/cn0561/common/cn0561_bd.tcl +++ b/projects/cn0561/common/cn0561_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/cn0561/coraz7s/Makefile b/projects/cn0561/coraz7s/Makefile index b29332afe30..469b3746537 100644 --- a/projects/cn0561/coraz7s/Makefile +++ b/projects/cn0561/coraz7s/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2023, 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/cn0561/zed/Makefile b/projects/cn0561/zed/Makefile index b590620a959..e64c6c4af2a 100755 --- a/projects/cn0561/zed/Makefile +++ b/projects/cn0561/zed/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2023, 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/pulsar_adc/common/pulsar_adc_bd.tcl b/projects/pulsar_adc/common/pulsar_adc_bd.tcl index 7ee4c31dbaa..bd70b18f781 100644 --- a/projects/pulsar_adc/common/pulsar_adc_bd.tcl +++ b/projects/pulsar_adc/common/pulsar_adc_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ###############################################################################