From 789fe5f0b9f0a2e176743d6bc66d47644d152938 Mon Sep 17 00:00:00 2001 From: bluncan Date: Thu, 16 Jan 2025 08:50:20 +0200 Subject: [PATCH 1/5] doc: projects: ad9084: initial commit --- docs/projects/ad9084_fmc/ad9084_204c_M4L8.svg | 3256 +++++++++++ .../ad9084_204c_M4L8_asymmetric.svg | 4958 +++++++++++++++++ .../ad9084_fmc/ad9084_clock_scheme_vcu118.svg | 3383 +++++++++++ docs/projects/ad9084_fmc/index.rst | 917 +++ docs/projects/index.rst | 1 + 5 files changed, 12515 insertions(+) create mode 100644 docs/projects/ad9084_fmc/ad9084_204c_M4L8.svg create mode 100644 docs/projects/ad9084_fmc/ad9084_204c_M4L8_asymmetric.svg create mode 100644 docs/projects/ad9084_fmc/ad9084_clock_scheme_vcu118.svg create mode 100644 docs/projects/ad9084_fmc/index.rst diff --git a/docs/projects/ad9084_fmc/ad9084_204c_M4L8.svg b/docs/projects/ad9084_fmc/ad9084_204c_M4L8.svg new file mode 100644 index 00000000000..414c667186a --- /dev/null +++ b/docs/projects/ad9084_fmc/ad9084_204c_M4L8.svg @@ -0,0 +1,3256 @@ + + + + + Example block design for Single Link; M=4; L=8; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + Example block design for Single Link; M=4; L=8; + + + + + + + + + + + + + + + + DmaClk=250MHz + + MEMORY INTERCONNECT + + VCU118 + + FMC+ CONNECTOR + AXI DMA + + + + UTIL_CPACK + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Receive data path + UTIL_ADC FIFO + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + MicroBlaze + Timer + + + + + + + + + RX JESD 204C LINK LAYER + + + RX JESD TPL + + 16x64bits@312.5MHz + + + + 8x20.625 Gbps + 8x20.625 Gbps + 8x20.625 Gbps + + + + + + + + 1024bits@312.5MHz + + + + + + REFCLK + SYSREF + + + 8 channels x8 samples + 1024bits@250MHz + 8 x8 samples + + Transmit data path + 1024bits@312.5MHz + + + + + AXI DMA + + + + UTIL_UPACK + UTIL_DAC FIFO + + + + + + + TX JESD 204C LINK LAYER + + TX JESD TPL + + 16x64bits@312.5MHz + + + + 8x20.625 Gbps + + + + + + + + 1024bits@312.5MHz + + + + + + 8 channels x8 samples + 1024bits@250MHz + 8 x8 samples + 1024bits@312.5MHz + TxDeviceClock=LaneRate/66=312.5MHz + TxLaneRate = 20.625 Gbps + RxLaneRate = 20.625Gbps + L=16; M=8; F=1; S=1; NP=16 + L=16; M=8; F=1; S=1; NP=16 + RxDeviceClock=LaneRate/66=312.5MHz + TX_DEVICE_CLK + + RX_DEVICE_CLK + + SystemClk=100MHz + + + + XCVR + Apollo A Side + Apollo B Side + + + diff --git a/docs/projects/ad9084_fmc/ad9084_204c_M4L8_asymmetric.svg b/docs/projects/ad9084_fmc/ad9084_204c_M4L8_asymmetric.svg new file mode 100644 index 00000000000..4e5adfd86ed --- /dev/null +++ b/docs/projects/ad9084_fmc/ad9084_204c_M4L8_asymmetric.svg @@ -0,0 +1,4958 @@ + + + + + Example block design for Single Link; M=4; L=8; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + Example block design for Single Link; M=4; L=8; + + + + + + + + + + + + + + + + DmaClk=250MHz + + + VCU118 + AXI DMA + + + + UTIL_CPACK + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Receive data path + UTIL_ADC FIFO + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + MicroBlaze + Timer + + + + + + + + + RX JESD 204C LINK LAYER + + + RX JESD TPL + + 8x64bits@312.5MHz + + + 8x20.625 Gbps + 8x20.625 Gbps + 8x20.625 Gbps + + + + + + + + + + + + + + + 512bits@312.5MHz + + + + + + REFCLK + SYSREF + + + 4 channels x8 samples + 512bits@250MHz + 4 x8 samples + + Transmit data path + 512bits@312.5MHz + + + + + AXI DMA + + + + UTIL_UPACK + UTIL_DAC FIFO + + + + + + + TX JESD 204C LINK LAYER + + TX JESD TPL + + 8x64bits@312.5MHz + + + + + + + + + + + + + + + + + 512bits@312.5MHz + + + + + + + 4 channels x8 samples + 512bits@250MHz + 4 x8 samples + 512bits@312.5MHz + TxDeviceClock=LaneRate/66=312.5MHz + TxLaneRate = 20.625 Gbps + Apollo B Side + Apollo A Side + RxLaneRate = 20.625Gbps + RxBLaneRate = 20.625Gbps + L=8; M=4; F=1; S=1; NP=16 + L=8; M=4; F=1; S=1; NP=16 + RxDeviceClock=LaneRate/66=312.5MHz + TX_DEVICE_CLK + + RX_DEVICE_CLK + + SystemClk=100MHz + + + + + + + + + + + + UTIL_ADC FIFO + DmaClk=250MHz + AXI DMA + + + + UTIL_CPACK + + + + + + + + RX JESD 204C LINK LAYER + + + RX JESD TPL + + 8x64bits@312.5MHz + + + 8x20.625 Gbps + + + + + + + + + + + + + + + 512bits@312.5MHz + + + + + + REFCLK_B + SYSREF_B + + + 4 channels x8 samples + 4 channels x8 samples + 512bits@250MHz + 4 x8 samples + 512bits@312.5MHz + + + + + AXI DMA + + + + UTIL_UPACK + UTIL_DAC FIFO + + + + + + + TX JESD 204C LINK LAYER + + TX JESD TPL + + 8x64bits@312.5MHz + + + + + + + + + + + + + + + + + 512bits@312.5MHz + + + + + + 512bits@250MHz + TxBDeviceClock=LaneRate/66=312.5MHz + TxBLaneRate = 20.625 Gbps + L=8; M=4; F=1; S=1; NP=16 + L=8; M=4; F=1; S=1; NP=16 + RxBDeviceClock=LaneRate/66=312.5MHz + TX_B_DEVICE_CLK + + RX_B_DEVICE_CLK + + SystemClk=100MHz + + + + XCVR + XCVR + + + MEMORY INTERCONNECT + + FMC+ CONNECTOR + 4 x8 samples + + diff --git a/docs/projects/ad9084_fmc/ad9084_clock_scheme_vcu118.svg b/docs/projects/ad9084_fmc/ad9084_clock_scheme_vcu118.svg new file mode 100644 index 00000000000..fd64fbaa6be --- /dev/null +++ b/docs/projects/ad9084_fmc/ad9084_clock_scheme_vcu118.svg @@ -0,0 +1,3383 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + HMC_7044 + + + FPGA + + + + + + G36,37 + H4,5 + G2,3 + D4,5 + sysref_in + + CLKOUT10 + + CLKOUT3 + CLKOUT8 + VCU118 + AD9084-FMC + + + + + + + ref_clk + + ref_clk_replica + + rx_sysref + + tx_sysref + VCU118 + + + SLR2 + + + + SLR0 + + + + SLR1 + + + + + + + + 126 + + + + + + + DDR_CTRL + + + + + + + + 121 + + + + + + + + CLKOUT10 + + + + CLKOUT11 + RX_B_DEVICE_CLK + + CLKOUT12 + TX_B_DEVICE_CLK + + CLKOUT9 + RX_DEVICE_CLK + + CLKOUT8 + TX_DEVICE_CLK + REF_CLK + + + RX/TX0 + RX/TX1 + clk_m2c[1] + + CLKOUT9 + CLKOUT11 + CLKOUT12 + clk_m2c[0] + SYSREF + CLKOUT_9 + CLKOUT_8 + FPGA_REFCLK + FMCP + + + clkin1 + ref_clk[0] + + tx_device_clk + + clkin0 + rx_device_clk + + sysref + GBTCLK0_M2C + MGTREFCLK0P_121 + CLK1_M2C + CLK0_M2C + CLK0_M2C + IO_L14P_T2L_N2_GC_45 + IO_L13P_T2L_N0_GC_QBC_43 + IO_L19P_T3L_N0_DBC_AD9P_45 + MGTREFCLK0P_126 + MGTREFCLK0P_121 + + L12,13 + B20,B21 + + ref_clk[1] + + ref_clk[2] + CLKOUT_12 + CLKOUT_11 + + clkin2 + rx_b_device_clk + + clkin3 + tx_b_device_clk + GBTCLK1_M2C + GBTCLK2_M2C + MGTREFCLK1P_120 + MGTREFCLK1P_122 + ref_clk[0] + + diff --git a/docs/projects/ad9084_fmc/index.rst b/docs/projects/ad9084_fmc/index.rst new file mode 100644 index 00000000000..7b2729bc542 --- /dev/null +++ b/docs/projects/ad9084_fmc/index.rst @@ -0,0 +1,917 @@ +.. _ad9084_fmc: + +Apollo (AD9084) HDL project +=============================================================================== + +Overview +------------------------------------------------------------------------------- + +The :adi:`AD9084-EBZ ` reference design +(also known as Apollo) is a processor based +(e.g. Microblaze) embedded system. +This reference design works with :adi:`EVAL-AD9084`. +The design consists from a receive and a transmit chain. + +The **receive chain** transports the captured samples from ADC to the system +memory (DDR). Before transferring the data to DDR, the samples are stored +in a buffer implemented on BRAMs from the FPGA fabric +(:git-hdl:`util_adcfifo `). +The space allocated in the buffer for each channel +depends on the number of currently active channels. It goes up to M x +64k samples if a single channel is selected or 64k samples per channel +if all channels are selected. + +The **transmit chain** transports samples from the system memory to the DAC +devices. Before streaming out the data to the DAC through the JESD link, +the samples first are loaded into a buffer +(:git-hdl:`util_dacfifo `) which will +cyclically stream the samples at the ``tx_device_clk`` data rate. The space +allocated in the transmit buffer for each channel depends on the number +of currently active channels. It goes up to M x 64k samples if a single +channel is selected or 64k samples per channel if all channels are +selected. + +All cores from the receive and transmit chains are programmable through +an AXI-Lite interface. + +The transmit and receive chains can operate at different data rates +having separate ``rx_device_clk``/``tx_device_clk`` and corresponding lane rates +but must share the same reference clock. + +Supported boards +------------------------------------------------------------------------------- + +- :adi:`AD9084-EBZ ` + +Supported devices +------------------------------------------------------------------------------- + +- :adi:`AD9084` + +Supported carriers +------------------------------------------------------------------------------- + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 1 + + * - Evaluation board + - Carrier + - FMC slot + - Maximum number of lanes + * - :adi:`AD9084-EBZ ` + - :intel:`FM87 ` + - FMCB + - 16 (8 per Apollo side) + * - + - :xilinx:`VCU118` + - FMC+ + - 24 (12 per Apollo side) + * - + - :xilinx:`VCU128` + - FMC+ + - 24 (12 per Apollo side) + * - + - :xilinx:`VCK190` + - FMC2 + - 8 (4 per Apollo side) + * - + - :xilinx:`VPK180` + - FMC+ + - 8 (4 per Apollo side) + +Block design +------------------------------------------------------------------------------- +.. important:: + + The Apollo chip is split into two sides, each side having up to 12 JESD lanes and 4 converters: + - Side A + - Side B + + The ``ASYMMETRIC_A_B_MODE`` parameter is used to enable the asymmetric A/B mode + where each Apollo side has a separate JESD link inside the block design. + + If the ASYMMETRIC_A_B_MODE parameter is set to 0, the block design will merge + the two sides into a single link. + + Given the following JESD204 configuration and assuming that **ASYMMETRIC_A_B_MODE = 0**: + - L = 8 + - M = 4 + - S = 1 + - N = NP = 16 + - **NUM_LINKS = 2** + + The resulted design will configure each Apollo side with the following parameters, but will merge the two sides into a single JESD link inside the design: + - L = 8 + - M = 4 + - S = 1 + - N = NP = 16 + + If however, **NUM_LINKS = 1**, the design will configure each side with the following parameters: + - L = 4 + - M = 2 + - S = 1 + - N = NP = 16 + + Given the following JESD204 configuration and assuming that **ASYMMETRIC_A_B_MODE = 1**: + - L = 8 + - M = 4 + - S = 1 + - N = NP = 16 + - **NUM_LINKS is ignored** + + The resulted design will configure each Apollo side with the following parameters, each having it's own JESD link inside the design: + - L = 8 + - M = 4 + - S = 1 + - N = NP = 16 + +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The data path and clock domains are depicted in the below diagrams: + +Example block design for ASYMMETRIC_A_B_MODE=0; M=4; L=8; NUM_LINKS=2; JESD204C +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ad9084_204c_M4L8.svg + :width: 800 + :align: center + :alt: AD9084-FMC JESD204C ASYMMETRIC_A_B_MODE=0 M=4 L=8 NUM_LINKS=2 block diagram + +.. warning:: + + **Build instructions:** + + The project must be built with the following parameters: + + .. shell:: bash + + $make JESD_MODE=64B66B \ + $ RX_LANE_RATE=20.625 \ + $ TX_LANE_RATE=20.625 \ + $ RX_JESD_M=4 \ + $ RX_JESD_L=8 \ + $ RX_JESD_S=1 \ + $ RX_JESD_NP=16 \ + $ RX_NUM_LINKS=2 \ + $ TX_JESD_M=4 \ + $ TX_JESD_L=8 \ + $ TX_JESD_S=1 \ + $ TX_JESD_NP=16 \ + $ TX_NUM_LINKS=2 \ + $ ASYMMETRIC_A_B_MODE=0 + +The Rx link is operating with the following parameters on each Apollo side: + +- Rx Deframer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Mode 47) +- Sample Rate: 2500 MSPS +- RX_DEVICE_CLK: 312.5 MHz (Lane Rate/66) +- REF_CLK: 625 MHz (Lane Rate/33) +- JESD204C Lane Rate: 20.625 Gbps +- QPLL1 + +The Tx link is operating with the following parameters: + +- Tx Framer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Mode 47) +- Sample Rate: 2500 MSPS +- Dual link: No +- TX_DEVICE_CLK: 312.5 MHz (Lane Rate/66) +- REF_CLK: 625 MHz (Lane Rate/33) +- JESD204C Lane Rate: 20.625 Gbps +- QPLL1 + +.. important:: + Because of the two Apollo sides, the total number of lanes in the design is 16 and the total number of converters is 8. + +Example block design for ASYMMETRIC_A_B_MODE=1; M=4; L=8; JESD204C +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ad9084_204c_M4L8_asymmetric.svg + :width: 800 + :align: center + :alt: AD9084-FMC JESD204C ASYMMETRIC_A_B_MODE=1 M=4 L=8 NUM_LINKS=2 block diagram + +.. warning:: + + **Build instructions:** + + The project must be built with the following parameters: + + .. shell:: bash + + $make JESD_MODE=64B66B \ + $ RX_LANE_RATE=20.625 \ + $ TX_LANE_RATE=20.625 \ + $ RX_JESD_M=4 \ + $ RX_JESD_L=8 \ + $ RX_JESD_S=1 \ + $ RX_JESD_NP=16 \ + $ TX_JESD_M=4 \ + $ TX_JESD_L=8 \ + $ TX_JESD_S=1 \ + $ TX_JESD_NP=16 \ + $ ASYMMETRIC_A_B_MODE=1 \ + $ RX_B_LANE_RATE=20.625 \ + $ TX_B_LANE_RATE=20.625 \ + $ RX_B_JESD_M=4 \ + $ RX_B_JESD_L=8 \ + $ RX_B_JESD_S=1 \ + $ RX_B_JESD_NP=16 \ + $ TX_B_JESD_M=4 \ + $ TX_B_JESD_L=8 \ + $ TX_B_JESD_S=1 \ + $ TX_B_JESD_NP=16 + + +The Rx link is operating with the following parameters on each Apollo side: + +- Rx Deframer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Mode 47) +- Sample Rate: 2500 MSPS +- RX_DEVICE_CLK: 312.5 MHz (Lane Rate/66) +- REF_CLK: 625 MHz (Lane Rate/33) +- JESD204C Lane Rate: 20.625 Gbps +- QPLL1 + +The Tx link is operating with the following parameters: + +- Tx Framer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Mode 47) +- Sample Rate: 2500 MSPS +- Dual link: No +- TX_DEVICE_CLK: 312.5 MHz (Lane Rate/66) +- REF_CLK: 625 MHz (Lane Rate/33) +- JESD204C Lane Rate: 20.625 Gbps +- QPLL1 + +Configuration modes +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The block design supports configuration of parameters and scales. + +We have listed a couple of examples at section +`Building the HDL project`_ and the default modes +for each project. + +.. note:: + + The parameters for Rx or Tx links can be changed from the + **system_project.tcl** file, located in + hdl/projects/ad9084_fmc/$CARRIER/system_project.tcl + +.. important:: + + For JESD204B: + + .. math:: + + Lane Rate = \frac{IQ Sample Rate * M * NP * \frac{10}{8}}{L} + + For JESD204C: + + .. math:: + + Lane Rate = \frac{IQ Sample Rate * M * NP * \frac{66}{64}}{L} + +The following are the parameters of this project that can be configured: + +- JESD_MODE: used link layer encoder mode + + - 64B66B - 64b66b link layer defined in JESD204C, uses ADI IP as Physical + Layer (except for Versal / Intel) + - 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical + Layer +- HSCI_ENABLE: enables the HSCI IP (Xilinx only) +- ASYMMETRIC_A_B_MODE: enables the asymmetric A/B mode where each Apollo side has a separate JESD link (Xilinx only) +- RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA) (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE) (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- REF_CLK_RATE: the rate of the reference clock (Versal and Intel only) +- DEVICE_CLK_RATE: the rate of the device clock (Intel only) +- [RX/TX]_JESD_M: number of converters per link (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- [RX/TX]_JESD_L: number of lanes per link (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- [RX/TX]_JESD_S: number of samples per frame (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- [RX/TX]_JESD_NP: number of bits per sample (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- [RX/TX]_NUM_LINKS: number of links (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in + kilosamples per converter (M) (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- RX_B_LANE_RATE: lane rate of the Rx link (MxFE to FPGA) (B link) +- TX_B_LANE_RATE: lane rate of the Tx link (FPGA to MxFE) (B link) +- [RX/TX]_B_JESD_M: number of converters per link (B link) +- [RX/TX]_B_JESD_L: number of lanes per link (B link) +- [RX/TX]_B_JESD_S: number of samples per frame (B link) +- [RX/TX]_B_JESD_NP: number of bits per sample (B link) +- [RX/TX]_B_NUM_LINKS: number of links (B link) +- [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in + kilosamples per converter (M) (B link) + +Clock scheme +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The clock sources depend on the carrier that is used: + +:xilinx:`VCU118` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ad9084_clock_scheme_vcu118.svg + :width: 800 + :align: center + :alt: AD9084-FMCA-EBZ VCU118 clock scheme + +Limitations +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. warning:: + + For the parameter selection, the following restrictions apply: + + - NP = 8, 12, 16 + - F = 1, 2, 3, 4, 6, 8 + - :ref:`JESD204B/C Link Rx peripheral > restrictions ` + - :ref:`JESD204B/C Link Tx peripheral > restrictions ` + +CPU/Memory interconnects addresses +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The addresses are dependent on the architecture of the FPGA, having an offset +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). + +Depending on the values of parameters $ASYMMETRIC_A_B_MODE, $ADI_PHY_SEL and $HSCI_ENABLE, +some IPs are instatiated and some are not. + +Check-out the table below to find out the conditions. + +========================= ========================================= =============== ============ +Instance Depends on parameter Microblaze ZynqMP +========================= ========================================= =============== ============ +apollo_rx_xcvr $ADI_PHY_SEL==1 0x44A6_0000 N/A +apollo_rx_jesd 0x44A9_0000 0xA4A9_0000 +rx_apollo_tpl_core 0x44A1_0000 0xA4A1_0000 +apollo_rx_dma 0x7C42_0000 0xBC42_0000 +apollo_rx_data_offload 0x7C45_0000 0xBC45_0000 +apollo_rx_b_xcvr $ADI_PHY_SEL==1 & $ASYMMETRIC_A_B_MODE==1 0x44AA_0000 N/A +apollo_rx_b_jesd $ASYMMETRIC_A_B_MODE==1 0x44AC_0000 0xA4AC_0000 +rx_b_apollo_tpl_core $ASYMMETRIC_A_B_MODE==1 0x44AB_0000 0xA4AB_0000 +apollo_rx_b_dma $ASYMMETRIC_A_B_MODE==1 0x7C47_0000 0xBC47_0000 +apollo_rx_b_data_offload $ASYMMETRIC_A_B_MODE==1 0x7C4A_0000 0xBC4A_0000 +apollo_tx_xcvr $ADI_PHY_SEL==1 0x44B6_0000 N/A +apollo_tx_jesd 0x44B9_0000 0xA4B9_0000 +tx_apollo_tpl_core 0x44B1_0000 0xA4B1_0000 +apollo_tx_dma 0x7C43_0000 0xBC43_0000 +apollo_tx_data_offload 0x7C44_0000 0xBC44_0000 +apollo_tx_b_xcvr $ADI_PHY_SEL==1 & $ASYMMETRIC_A_B_MODE==1 0x44BA_0000 N/A +apollo_tx_b_jesd $ASYMMETRIC_A_B_MODE==1 0x44BC_0000 0xA4BC_0000 +tx_b_apollo_tpl_core $ASYMMETRIC_A_B_MODE==1 0x44BB_0000 0xA4BB_0000 +apollo_tx_b_dma $ASYMMETRIC_A_B_MODE==1 0x7C48_0000 0xBC48_0000 +apollo_tx_b_data_offload $ASYMMETRIC_A_B_MODE==1 0x7C49_0000 0xBC44_0000 +axi_hsci $HSCI_ENABLE==1 0x7C50_0000 0xBC50_0000 +axi_hsci_clkgen $HSCI_ENABLE==1 0x44AD_0000 0xA4AD_0000 +axi_spi_2 0x44A8_0000 0xA4A8_0000 +========================= ========================================= =============== ============ + +For the Intel carriers, only a part of the CPU interrupts are specified, +as the rest depend on the values of $TX_NUM_OF_LANES +(see :git-hdl:`projects/ad9084_fmc/common/ad9084_fmcb_ebz_qsys.tcl` +for more details). + +================================== =========== +Instance Intel +================================== =========== +apollo_rx_jesd204.link_reconfig 0x000C_0000 +apollo_rx_jesd204.link_management 0x000C_4000 +apollo_tx_jesd204.link_reconfig 0x000C_8000 +apollo_tx_jesd204.link_management 0x000C_C000 +apollo_rx_tpl.s_axi 0x000D_2000 +apollo_tx_tpl.s_axi 0x000D_4000 +apollo_rx_dma.s_axi 0x000D_8000 +apollo_tx_dma.s_axi 0x000D_C000 +apollo_gpio.s1 0x000E_0000 +apollo_spi.spi_control_port 0x000E_A000 +================================== =========== + +SPI connections +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 1 + + * - SPI type + - SPI manager instance + - SPI subordinate + - CS + * - PS + - spi0 + - ADF4382 + - 0 + * - PS + - spi0 + - HMC7044 + - 1 + * - PL + - axi_spi_2 + - AD9084 + - 0 + +GPIOs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following table lists the GPIO signals used in this project that +are connected to the Apollo evaluation board and are common between +all the carriers. + +.. list-table:: + :widths: 20 20 20 20 20 + :header-rows: 2 + + * - Apollo GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + - Software GPIO + * - + - (from FPGA view) + - + - Microblaze + - ZynqMP + * - resetb + - OUT + - 62 + - 62 + - 30 + * - trig_b[1:0] + - OUT + - 61:60 + - 61:60 + - 29:28 + * - trig_a[1:0] + - OUT + - 59:58 + - 59:58 + - 27:26 + * - trig_in + - IN + - 53 + - 53 + - 21 + * - aux_gpio + - INOUT + - 48 + - 48 + - 16 + * - gpio[30:15] + - INOUT + - 47:32 + - 47:32 + - 15:0 + +The following table lists the GPIO signals that are only present +in the Versal projects. + +They are used from the linux kernel to +control the reset sequence of the GTY/GTYP transceivers. + +.. list-table:: + :widths: 40 20 20 20 + :header-rows: 2 + + * - Versal transceivers GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + * - + - (from FPGA view) + - + - ZynqMP + * - tx_reset_datapath + - IN + - 71 + - 39 + * - rx_reset_datapath + - IN + - 70 + - 38 + * - tx_reset_pll_and_datapath + - IN + - 69 + - 37 + * - rx_reset_pll_and_datapath + - IN + - 68 + - 36 + * - gt_reset + - IN + - 67 + - 35 + * - mst_resetdone + - OUT + - 66 + - 34 + * - tx_resetdone + - OUT + - 65 + - 33 + * - rx_resetdone + - OUT + - 64 + - 32 + * - tx_b_reset_datapath + - IN + - 79 + - 47 + * - rx_b_reset_datapath + - IN + - 78 + - 46 + * - tx_b_reset_pll_and_datapath + - IN + - 77 + - 45 + * - rx_b_reset_pll_and_datapath + - IN + - 76 + - 44 + * - gt_b_reset + - IN + - 75 + - 43 + * - mst_b_resetdone + - OUT + - 74 + - 42 + * - tx_b_resetdone + - OUT + - 73 + - 41 + * - rx_b_resetdone + - OUT + - 72 + - 40 + +The following table lists the GPIOs that are only preset on the Intel +carriers. + +.. list-table:: + :widths: 40 20 20 20 + :header-rows: 2 + + * - Intel GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + * - + - (from FPGA view) + - + - ZynqMP + * - tx_fifo_bypass_bypass + - IN + - 63 + - 31 + +Interrupts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Below are the Programmable Logic interrupts used in this project. + +==================== === ================ ============ +Instance name HDL Linux Microblaze Linux ZynqMP +==================== === ================ ============ +axi_apollo_rx_dma 13 13 97 +axi_apollo_tx_dma 12 12 96 +axi_apollo_rx_jesd 11 11 95 +axi_apollo_tx_jesd 10 10 94 +axi_spi_2 9 9 93 +axi_apollo_rx_b_dma 4 4 88 +axi_apollo_tx_b_dma 3 3 87 +axi_apollo_rx_b_jesd 2 2 86 +axi_apollo_tx_b_jesd 1 1 85 +==================== === ================ ============ + +Building the HDL project +------------------------------------------------------------------------------- + +The design is built upon ADI's generic HDL reference design framework. +ADI distributes the bit/elf files of these projects as part of the +:dokuwiki:`ADI Kuiper Linux `. +If you want to build the sources, ADI makes them available on the +:git-hdl:`HDL repository `. To get the source you must +`clone `__ +the HDL repository. + +Then go to the :git-hdl:`projects/ad9084_fmc` +location and run the make command by typing in you command prompt: + +Example for building the project with parameters: + +**Linux/Cygwin/WSL** + +.. shell:: + :show-user: + + $cd hdl/projects/ad9084_fmc/vck190 + $make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 \ + $ RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 \ + $ RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 \ + $ TX_JESD_S=1 TX_JESD_NP=16 + +The following dropdowns contain tables with the parameters that can be used to +configure this project, depending on the carrier used. +Where a cell contains a --- (dash) it means that the parameter doesn't exist +for that project (ad9084_fmc/$carrier). + +.. warning:: + + For the parameter selection, the following restrictions apply: + + - NP = 8, 12, 16 + - F = 1, 2, 3, 4, 6, 8 + - :ref:`JESD204B/C Link Rx peripheral > restrictions ` + - :ref:`JESD204B/C Link Tx peripheral > restrictions ` + + ``NP`` notation is equivalent with ``N'`` + +.. collapsible:: Default values of the make parameters for AD9084-EBZ + + +---------------------+----------+--------+--------+--------+-------+ + | Parameter | Default value of the parameters | + | +--------+--------+---------+--------+--------+ + | | FM87 | VCU118 | VCU128 | VCK190 | VPK180 | + +---------------------+--------+--------+---------+--------+--------+ + | JESD_MODE | 64B66B | 64B66B | 64B66B | 64B66B | 64B66B | + +---------------------+--------+--------+---------+--------+--------+ + | ENABLE_HSCI |:red:`-`| 1 | :red:`-`| 1* | 1* | + +---------------------+--------+--------+---------+--------+--------+ + | REF_CLK_RATE* | 312.5 | --- | --- | 312.5 | 312.5 | + +---------------------+--------+--------+---------+--------+--------+ + | DEVICE_CLK_RATE** | 312.5 | --- | --- | --- | --- | + +---------------------+--------+--------+---------+--------+--------+ + | RX_LANE_RATE | 20.625 | 20.625 | 10.3125 | 20.625 | 20.625 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_LANE_RATE | 20.625 | 20.625 | 10.3125 | 20.625 | 20.625 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_JESD_M | 4 | 4 | 4 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_JESD_L | 8 | 8 | 8 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_JESD_S | 1 | 1 | 1 | 1 | 1 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_JESD_NP | 16 | 16 | 16 | 16 | 16 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_NUM_LINKS | 2 | 1 | 1 | 2 | 2 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_JESD_M | 4 | 4 | 4 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_JESD_L | 8 | 8 | 8 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_JESD_S | 1 | 1 | 1 | 1 | 1 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_JESD_NP | 16 | 16 | 16 | 16 | 16 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_NUM_LINKS | 2 | 1 | 1 | 2 | 2 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_KS_PER_CHANNEL | 16 | 32 | 65536 | 64 | 64 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_KS_PER_CHANNEL | 16 | 32 | 65536 | 64 | 64 | + +---------------------+--------+--------+---------+--------+--------+ + | ASYMMETRIC_A_B_MODE |:red:`-`| 1 | 1 | 0 | 0 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_B_LANE_RATE |:red:`-`| 20.625 | 10.3125 | 20.625 | 20.625 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_B_LANE_RATE |:red:`-`| 20.625 | 10.3125 | 20.625 | 20.625 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_B_JESD_M |:red:`-`| 4 | 4 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_B_JESD_L |:red:`-`| 8 | 8 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_B_JESD_S |:red:`-`| 1 | 1 | 1 | 1 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_B_JESD_NP |:red:`-`| 16 | 16 | 16 | 16 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_B_JESD_M |:red:`-`| 4 | 4 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_B_JESD_L |:red:`-`| 8 | 8 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_B_JESD_S |:red:`-`| 1 | 1 | 1 | 1 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_B_JESD_NP |:red:`-`| 16 | 16 | 16 | 16 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_B_KS_PER_CHANNEL |:red:`-`| 32 | 65536 | 64 | 64 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_B_KS_PER_CHANNEL |:red:`-`| 32 | 65536 | 64 | 64 | + +---------------------+--------+--------+---------+--------+--------+ + | ADC_DO_MEM_TYPE | --- | --- | 2 | --- | --- | + +---------------------+--------+--------+---------+--------+--------+ + | DAC_DO_MEM_TYPE | --- | --- | 2 | --- | --- | + +---------------------+--------+--------+---------+--------+--------+ + + .. admonition:: Legend + :class: note + + :red:`-` --- this feature is not supported + + `*` --- can be disabled + +The result of the build, if parameters were used, will be in a folder named +by the configuration used: + +if the following command was run + +``make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16`` + +then the folder name will be: + +``RXRATE2_5_TXRATE2_5_RXL8_RXM4_RXS1_RXNP16_TXL8_TXM4_TXS1_TXNP16`` +because of truncation of some keywords so the name will not exceed the limits +of the Operating System (``JESD``, ``LANE``, etc. are removed) of 260 +characters. + +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. + +Software considerations +------------------------------------------------------------------------------- + +ADC - crossbar config +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Due to physical constraints, Rx lanes are reordered as described in the +following table. + +e.g physical lane 2 from ADC from A side connects to logical lane 1 +from the VCU118. Therefore the crossbar from the device must be set +accordingly. + +============== =============== =============== =============== =============== +ADC A phy Lane VCU118 VCU128 VCK190 / VPK180 FM87 +============== =============== =============== =============== =============== +0 7 11 5 11 +1 5 3 1 9 +2 1 8 3 8 +3 2 9 7 10 +4 11 7 N/C 7 +5 3 5 N/C 3 +6 8 1 N/C 1 +7 9 2 N/C 5 +8 10 10 N/C N/C +9 6 6 N/C N/C +10 4 4 N/C N/C +11 0 0 N/C N/C +============== =============== =============== =============== =============== + +============== =============== =============== =============== =============== +ADC B phy Lane VCU118 VCU128 VCK190 / VPK180 FM87 +============== =============== =============== =============== =============== +0 10 3 1 11 +1 6 2 7 9 +2 4 5 10 8 +3 0 7 3 5 +4 3 8 N/C 3 +5 2 1 N/C 10 +6 5 11 N/C 7 +7 7 9 N/C 1 +8 8 10 N/C N/C +9 1 6 N/C N/C +10 11 4 N/C N/C +11 9 0 N/C N/C +============== =============== =============== =============== =============== + +DAC - crossbar config +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Due to physical constraints, Tx lanes are reordered as described in the +following table. + +e.g physical lane 2 from DAC from A side connects to logical lane 9 +from the VCU118. Therefore the crossbar from the device must be set +accordingly. + +============== =============== =============== =============== =============== +DAC A phy Lane VCU118 VCU128 VCK190 / VPK180 FM87 +============== =============== =============== =============== =============== +0 10 5 11 2 +1 8 1 3 1 +2 9 3 8 5 +3 11 7 9 7 +4 5 10 N/C 9 +5 1 8 N/C 8 +6 3 9 N/C 3 +7 7 11 N/C 11 +8 4 4 N/C N/C +9 6 6 N/C N/C +10 2 2 N/C N/C +11 0 0 N/C N/C +============== =============== =============== =============== =============== + +============== =============== =============== =============== =============== +DAC B phy Lane VCU118 VCU128 VCK190 / VPK180 FM87 +============== =============== =============== =============== =============== +0 4 1 3 9 +1 6 7 2 11 +2 2 10 5 1 +3 0 3 7 8 +4 1 5 N/C 7 +5 7 8 N/C 5 +6 10 9 N/C 2 +7 3 11 N/C 3 +8 5 4 N/C N/C +9 8 6 N/C N/C +10 9 2 N/C N/C +11 11 0 N/C N/C +============== =============== =============== =============== =============== + +Resources +------------------------------------------------------------------------------- + +Systems related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :dokuwiki:`[Wiki] AD9084 Prototyping Platform User Guide ` +- Here you can find all the quick start guides on wiki documentation + :dokuwiki:`[Wiki] AD9084 Quick Start Guides ` + +Here you can find the quick start guides available for these evaluation boards: + +.. list-table:: + :widths: 20 20 40 20 + :header-rows: 1 + + * - Evaluation board + - Microblaze + - Versal + - Agilex 7 + * - AD9084 + - :dokuwiki:`VCU118 ` + - :dokuwiki:`VCK190/VMK180/VPK180 ` + - :dokuwiki:`FM87 ` + + +Hardware related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Product datasheets: + + - :adi:`AD9084` +- `UG-1578, Device User Guide `__ +- `UG-1829, Evaluation Board User Guide `__ + +HDL related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-hdl:`ad9084_fmc HDL project source code ` + +.. list-table:: + :widths: 30 35 35 + :header-rows: 1 + + * - IP name + - Source code link + - Documentation link + * - AXI_DMAC + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` + * - AXI_SYSID + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` + * - SYSID_ROM + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` + * - UTIL_CPACK2 + - :git-hdl:`library/util_pack/util_cpack2` + - :ref:`util_cpack2` + * - UTIL_UPACK2 + - :git-hdl:`library/util_pack/util_upack2` + - :ref:`util_upack2` + * - UTIL_ADXCVR for AMD + - :git-hdl:`library/xilinx/util_adxcvr` + - :ref:`util_adxcvr` + * - AXI_ADXCVR for Intel + - :git-hdl:`library/intel/axi_adxcvr` + - :ref:`axi_adxcvr intel` + * - AXI_ADXCVR for AMD + - :git-hdl:`library/xilinx/axi_adxcvr` + - :ref:`axi_adxcvr amd` + * - AXI_JESD204_RX + - :git-hdl:`library/jesd204/axi_jesd204_rx` + - :ref:`axi_jesd204_rx` + * - AXI_JESD204_TX + - :git-hdl:`library/jesd204/axi_jesd204_tx` + - :ref:`axi_jesd204_tx` + * - JESD204_TPL_ADC + - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc` + - :ref:`ad_ip_jesd204_tpl_adc` + * - JESD204_TPL_DAC + - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` + - :ref:`ad_ip_jesd204_tpl_dac` + +- :dokuwiki:`[Wiki] Generic JESD204B block designs ` +- :ref:`jesd204` + +Software related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :dokuwiki:`[Wiki] AD9084-EBZ Linux driver wiki page ` +- Python support: + + - `AD9084 class documentation `__ + - `PyADI-IIO documentation `__ + +.. include:: ../common/more_information.rst + +.. include:: ../common/support.rst diff --git a/docs/projects/index.rst b/docs/projects/index.rst index 86caa2d8b57..19efcf71a56 100644 --- a/docs/projects/index.rst +++ b/docs/projects/index.rst @@ -51,6 +51,7 @@ Contents AD9081-FMCA-EBZ-X-BAND AD9083-EVB AD9084-EBZ + AD9084 AD916x-FMC AD9208-DUAL-EBZ AD9209-FMCA-EBZ From 83ab716aadd20c504dda814feab3a445372bbea3 Mon Sep 17 00:00:00 2001 From: bluncan Date: Mon, 27 Jan 2025 12:04:22 +0200 Subject: [PATCH 2/5] docs: projects: ad9084_fmca_ebz: Initial documentation Signed-off-by: bluncan --- .../ad9084_204c_M4L8.svg | 86 +++++++++-------- .../ad9084_204c_M4L8_asymmetric.svg | 94 ++++++++++--------- .../ad9084_clock_scheme_vcu118.svg | 0 .../{ad9084_fmc => ad9084_fmca_ebz}/index.rst | 32 +++---- docs/projects/index.rst | 2 +- 5 files changed, 117 insertions(+), 97 deletions(-) rename docs/projects/{ad9084_fmc => ad9084_fmca_ebz}/ad9084_204c_M4L8.svg (98%) rename docs/projects/{ad9084_fmc => ad9084_fmca_ebz}/ad9084_204c_M4L8_asymmetric.svg (99%) rename docs/projects/{ad9084_fmc => ad9084_fmca_ebz}/ad9084_clock_scheme_vcu118.svg (100%) rename docs/projects/{ad9084_fmc => ad9084_fmca_ebz}/index.rst (97%) diff --git a/docs/projects/ad9084_fmc/ad9084_204c_M4L8.svg b/docs/projects/ad9084_fmca_ebz/ad9084_204c_M4L8.svg similarity index 98% rename from docs/projects/ad9084_fmc/ad9084_204c_M4L8.svg rename to docs/projects/ad9084_fmca_ebz/ad9084_204c_M4L8.svg index 414c667186a..67dbb61f848 100644 --- a/docs/projects/ad9084_fmc/ad9084_204c_M4L8.svg +++ b/docs/projects/ad9084_fmca_ebz/ad9084_204c_M4L8.svg @@ -1197,7 +1197,7 @@ inkscape:connector-curvature="0" id="path4660-1-6-9-3-7" d="M 5.77,0 -2.88,5 V -5 Z" - style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1" transform="scale(-0.4)" /> VCU118 + x="666.10992" + y="22.671709" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:20px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial Bold';text-align:center;text-anchor:middle;fill:#000000;fill-opacity:0.858696;stroke-width:1px" + id="tspan3772">VCU118/VCU128/VCK190/VPK180/FM87 UTIL_CPACK UTIL_ADC FIFO + sodipodi:role="line">DATA_OFFLOAD MicroBlaze + sodipodi:role="line">MicroBlaze/ZynqMP UTIL_UPACK + x="-457.43048" + y="385.98578" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:17.5px;line-height:108%;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke:none;stroke-width:1px;stroke-opacity:1">UTIL_UPACK UTIL_DAC FIFO + x="-473.67392" + y="294.76489" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:17.5px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke:none;stroke-width:1px;stroke-opacity:1">DATA_OFFLOAD VCU118 + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:20px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial Bold';text-align:center;text-anchor:middle;fill:#000000;fill-opacity:0.858696;stroke-width:1px">VCU118/VCU128/VCK190/VPK180/FM87 UTIL_ADC FIFO + sodipodi:role="line">DATA_OFFLOAD MicroBlaze + sodipodi:role="line">MicroBlaze/ZynqMP UTIL_DAC FIFO + x="-472.96683" + y="294.76492" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:17.5px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke:none;stroke-width:1px;stroke-opacity:1">DATA_OFFLOAD UTIL_ADC FIFO + sodipodi:role="line">DATA_OFFLOAD UTIL_UPACK - UTIL_DAC FIFO 8 samples + DATA_OFFLOAD diff --git a/docs/projects/ad9084_fmc/ad9084_clock_scheme_vcu118.svg b/docs/projects/ad9084_fmca_ebz/ad9084_clock_scheme_vcu118.svg similarity index 100% rename from docs/projects/ad9084_fmc/ad9084_clock_scheme_vcu118.svg rename to docs/projects/ad9084_fmca_ebz/ad9084_clock_scheme_vcu118.svg diff --git a/docs/projects/ad9084_fmc/index.rst b/docs/projects/ad9084_fmca_ebz/index.rst similarity index 97% rename from docs/projects/ad9084_fmc/index.rst rename to docs/projects/ad9084_fmca_ebz/index.rst index 7b2729bc542..38a48604b22 100644 --- a/docs/projects/ad9084_fmc/index.rst +++ b/docs/projects/ad9084_fmca_ebz/index.rst @@ -1,12 +1,12 @@ -.. _ad9084_fmc: +.. _ad9084_fmca_ebz: -Apollo (AD9084) HDL project +AD9084 (Apollo) HDL project =============================================================================== Overview ------------------------------------------------------------------------------- -The :adi:`AD9084-EBZ ` reference design +The :adi:`AD9084-FMCA-EBZ ` reference design (also known as Apollo) is a processor based (e.g. Microblaze) embedded system. This reference design works with :adi:`EVAL-AD9084`. @@ -41,7 +41,7 @@ but must share the same reference clock. Supported boards ------------------------------------------------------------------------------- -- :adi:`AD9084-EBZ ` +- :adi:`AD9084-FMCA-EBZ ` evaluation board Supported devices ------------------------------------------------------------------------------- @@ -59,7 +59,7 @@ Supported carriers - Carrier - FMC slot - Maximum number of lanes - * - :adi:`AD9084-EBZ ` + * - :adi:`AD9084-FMCA-EBZ ` - :intel:`FM87 ` - FMCB - 16 (8 per Apollo side) @@ -256,7 +256,7 @@ for each project. The parameters for Rx or Tx links can be changed from the **system_project.tcl** file, located in - hdl/projects/ad9084_fmc/$CARRIER/system_project.tcl + hdl/projects/ad9084_fmca_ebz/$CARRIER/system_project.tcl .. important:: @@ -369,7 +369,7 @@ axi_spi_2 0x44A8_0000 For the Intel carriers, only a part of the CPU interrupts are specified, as the rest depend on the values of $TX_NUM_OF_LANES -(see :git-hdl:`projects/ad9084_fmc/common/ad9084_fmcb_ebz_qsys.tcl` +(see :git-hdl:`projects/ad9084_fmca_ebz/common/ad9084_fmca_ebz_qsys.tcl` for more details). ================================== =========== @@ -596,7 +596,7 @@ If you want to build the sources, ADI makes them available on the `clone `__ the HDL repository. -Then go to the :git-hdl:`projects/ad9084_fmc` +Then go to the :git-hdl:`projects/ad9084_fmca_ebz` location and run the make command by typing in you command prompt: Example for building the project with parameters: @@ -606,7 +606,7 @@ Example for building the project with parameters: .. shell:: :show-user: - $cd hdl/projects/ad9084_fmc/vck190 + $cd hdl/projects/ad9084_fmca_ebz/vck190 $make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 \ $ RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 \ $ RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 \ @@ -615,7 +615,7 @@ Example for building the project with parameters: The following dropdowns contain tables with the parameters that can be used to configure this project, depending on the carrier used. Where a cell contains a --- (dash) it means that the parameter doesn't exist -for that project (ad9084_fmc/$carrier). +for that project (ad9084_fmca_ebz/$carrier). .. warning:: @@ -628,7 +628,7 @@ for that project (ad9084_fmc/$carrier). ``NP`` notation is equivalent with ``N'`` -.. collapsible:: Default values of the make parameters for AD9084-EBZ +.. collapsible:: Default values of the make parameters for AD9084-FMCA-EBZ +---------------------+----------+--------+--------+--------+-------+ | Parameter | Default value of the parameters | @@ -822,9 +822,9 @@ Resources Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] AD9084 Prototyping Platform User Guide ` +- :dokuwiki:`[Wiki] AD9084 Prototyping Platform User Guide ` - Here you can find all the quick start guides on wiki documentation - :dokuwiki:`[Wiki] AD9084 Quick Start Guides ` + :dokuwiki:`[Wiki] AD9084 Quick Start Guides ` Here you can find the quick start guides available for these evaluation boards: @@ -839,7 +839,7 @@ Here you can find the quick start guides available for these evaluation boards: * - AD9084 - :dokuwiki:`VCU118 ` - :dokuwiki:`VCK190/VMK180/VPK180 ` - - :dokuwiki:`FM87 ` + - :dokuwiki:`FM87 ` Hardware related @@ -854,7 +854,7 @@ Hardware related HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`ad9084_fmc HDL project source code ` +- :git-hdl:`ad9084_fmca_ebz HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -906,7 +906,7 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] AD9084-EBZ Linux driver wiki page ` +- :dokuwiki:`[Wiki] AD9084-FMCA-EBZ Linux driver wiki page ` - Python support: - `AD9084 class documentation `__ diff --git a/docs/projects/index.rst b/docs/projects/index.rst index 19efcf71a56..061be415522 100644 --- a/docs/projects/index.rst +++ b/docs/projects/index.rst @@ -51,7 +51,7 @@ Contents AD9081-FMCA-EBZ-X-BAND AD9083-EVB AD9084-EBZ - AD9084 + AD9084-FMCA-EBZ AD916x-FMC AD9208-DUAL-EBZ AD9209-FMCA-EBZ From 8bc022eeea1831414a6eb29478f21c33183a0cfc Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Thu, 8 May 2025 11:34:46 +0200 Subject: [PATCH 3/5] docs: projects: ad9084_fmca_ebz: Table header, white-space Signed-off-by: Jorge Marques --- docs/projects/ad9084_fmca_ebz/index.rst | 90 ++++++++++++++----------- 1 file changed, 52 insertions(+), 38 deletions(-) diff --git a/docs/projects/ad9084_fmca_ebz/index.rst b/docs/projects/ad9084_fmca_ebz/index.rst index 38a48604b22..7b45b7414fd 100644 --- a/docs/projects/ad9084_fmca_ebz/index.rst +++ b/docs/projects/ad9084_fmca_ebz/index.rst @@ -85,8 +85,9 @@ Block design .. important:: The Apollo chip is split into two sides, each side having up to 12 JESD lanes and 4 converters: - - Side A - - Side B + + - Side A + - Side B The ``ASYMMETRIC_A_B_MODE`` parameter is used to enable the asymmetric A/B mode where each Apollo side has a separate JESD link inside the block design. @@ -95,36 +96,46 @@ Block design the two sides into a single link. Given the following JESD204 configuration and assuming that **ASYMMETRIC_A_B_MODE = 0**: - - L = 8 - - M = 4 - - S = 1 - - N = NP = 16 - - **NUM_LINKS = 2** - - The resulted design will configure each Apollo side with the following parameters, but will merge the two sides into a single JESD link inside the design: - - L = 8 - - M = 4 - - S = 1 - - N = NP = 16 - - If however, **NUM_LINKS = 1**, the design will configure each side with the following parameters: - - L = 4 - - M = 2 - - S = 1 - - N = NP = 16 - - Given the following JESD204 configuration and assuming that **ASYMMETRIC_A_B_MODE = 1**: - - L = 8 - - M = 4 - - S = 1 - - N = NP = 16 - - **NUM_LINKS is ignored** - - The resulted design will configure each Apollo side with the following parameters, each having it's own JESD link inside the design: - - L = 8 - - M = 4 - - S = 1 - - N = NP = 16 + + - L = 8 + - M = 4 + - S = 1 + - N = NP = 16 + - **NUM_LINKS = 2** + + The resulted design will configure each Apollo side with the following + parameters, but will merge the two sides into a single JESD link inside the + design: + + - L = 8 + - M = 4 + - S = 1 + - N = NP = 16 + + If however, **NUM_LINKS = 1**, the design will configure each side with the + following parameters: + + - L = 4 + - M = 2 + - S = 1 + - N = NP = 16 + + Given the following JESD204 configuration and assuming that + **ASYMMETRIC_A_B_MODE = 1**: + + - L = 8 + - M = 4 + - S = 1 + - N = NP = 16 + - **NUM_LINKS is ignored** + + The resulted design will configure each Apollo side with the following + parameters, each having it's own JESD link inside the design: + + - L = 8 + - M = 4 + - S = 1 + - N = NP = 16 Block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -146,6 +157,7 @@ Example block design for ASYMMETRIC_A_B_MODE=0; M=4; L=8; NUM_LINKS=2; JESD204C The project must be built with the following parameters: .. shell:: bash + :no-path: $make JESD_MODE=64B66B \ $ RX_LANE_RATE=20.625 \ @@ -199,6 +211,7 @@ Example block design for ASYMMETRIC_A_B_MODE=1; M=4; L=8; JESD204C The project must be built with the following parameters: .. shell:: bash + :no-path: $make JESD_MODE=64B66B \ $ RX_LANE_RATE=20.625 \ @@ -248,9 +261,8 @@ Configuration modes The block design supports configuration of parameters and scales. -We have listed a couple of examples at section -`Building the HDL project`_ and the default modes -for each project. +We have listed a couple of examples at section :ref:`ad9084_fmca_ebz build` and +the default modes for each project. .. note:: @@ -585,6 +597,8 @@ axi_apollo_rx_b_jesd 2 2 86 axi_apollo_tx_b_jesd 1 1 85 ==================== === ================ ============ +.. _ad9084_fmca_ebz build: + Building the HDL project ------------------------------------------------------------------------------- @@ -630,11 +644,11 @@ for that project (ad9084_fmca_ebz/$carrier). .. collapsible:: Default values of the make parameters for AD9084-FMCA-EBZ - +---------------------+----------+--------+--------+--------+-------+ + +---------------------+---------------------------------------------+ | Parameter | Default value of the parameters | | +--------+--------+---------+--------+--------+ | | FM87 | VCU118 | VCU128 | VCK190 | VPK180 | - +---------------------+--------+--------+---------+--------+--------+ + +=====================+========+========+=========+========+========+ | JESD_MODE | 64B66B | 64B66B | 64B66B | 64B66B | 64B66B | +---------------------+--------+--------+---------+--------+--------+ | ENABLE_HSCI |:red:`-`| 1 | :red:`-`| 1* | 1* | @@ -702,7 +716,7 @@ for that project (ad9084_fmca_ebz/$carrier). | DAC_DO_MEM_TYPE | --- | --- | 2 | --- | --- | +---------------------+--------+--------+---------+--------+--------+ - .. admonition:: Legend + .. admonition:: Legend :class: note :red:`-` --- this feature is not supported From c2e948abcd72e846041a9fb49af44b4c9cfc5ed8 Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Thu, 8 May 2025 11:57:38 +0200 Subject: [PATCH 4/5] docs/projects/ad9084_fmca_ebz: Merge with ad9084_ebz The project supports multiple evaluation boards, use the generic name. Signed-off-by: Jorge Marques --- .../ad9084_204c_M4L8.svg | 0 .../ad9084_204c_M4L8_asymmetric.svg | 0 .../ad9084_clock_scheme_vcu118.svg | 0 docs/projects/ad9084_ebz/index.rst | 878 ++++++++++++++++- docs/projects/ad9084_fmca_ebz/index.rst | 931 ------------------ docs/projects/index.rst | 1 - 6 files changed, 874 insertions(+), 936 deletions(-) rename docs/projects/{ad9084_fmca_ebz => ad9084_ebz}/ad9084_204c_M4L8.svg (100%) rename docs/projects/{ad9084_fmca_ebz => ad9084_ebz}/ad9084_204c_M4L8_asymmetric.svg (100%) rename docs/projects/{ad9084_fmca_ebz => ad9084_ebz}/ad9084_clock_scheme_vcu118.svg (100%) delete mode 100644 docs/projects/ad9084_fmca_ebz/index.rst diff --git a/docs/projects/ad9084_fmca_ebz/ad9084_204c_M4L8.svg b/docs/projects/ad9084_ebz/ad9084_204c_M4L8.svg similarity index 100% rename from docs/projects/ad9084_fmca_ebz/ad9084_204c_M4L8.svg rename to docs/projects/ad9084_ebz/ad9084_204c_M4L8.svg diff --git a/docs/projects/ad9084_fmca_ebz/ad9084_204c_M4L8_asymmetric.svg b/docs/projects/ad9084_ebz/ad9084_204c_M4L8_asymmetric.svg similarity index 100% rename from docs/projects/ad9084_fmca_ebz/ad9084_204c_M4L8_asymmetric.svg rename to docs/projects/ad9084_ebz/ad9084_204c_M4L8_asymmetric.svg diff --git a/docs/projects/ad9084_fmca_ebz/ad9084_clock_scheme_vcu118.svg b/docs/projects/ad9084_ebz/ad9084_clock_scheme_vcu118.svg similarity index 100% rename from docs/projects/ad9084_fmca_ebz/ad9084_clock_scheme_vcu118.svg rename to docs/projects/ad9084_ebz/ad9084_clock_scheme_vcu118.svg diff --git a/docs/projects/ad9084_ebz/index.rst b/docs/projects/ad9084_ebz/index.rst index 8837b714587..e53a228cb23 100644 --- a/docs/projects/ad9084_ebz/index.rst +++ b/docs/projects/ad9084_ebz/index.rst @@ -3,61 +3,931 @@ AD9084-EBZ (Apollo) HDL project =============================================================================== -.. attention:: - - This is a stub page, content will be updated shortly. - Overview ------------------------------------------------------------------------------- +The :adi:`AD9084-EBZ ` reference design +(also known as Apollo) is a processor based +(e.g. Microblaze) embedded system. +This reference design works with :adi:`EVAL-AD9084`. +The design consists from a receive and a transmit chain. + +The **receive chain** transports the captured samples from ADC to the system +memory (DDR). Before transferring the data to DDR, the samples are stored +in a buffer implemented on BRAMs from the FPGA fabric +(:git-hdl:`util_adcfifo `). +The space allocated in the buffer for each channel +depends on the number of currently active channels. It goes up to M x +64k samples if a single channel is selected or 64k samples per channel +if all channels are selected. + +The **transmit chain** transports samples from the system memory to the DAC +devices. Before streaming out the data to the DAC through the JESD link, +the samples first are loaded into a buffer +(:git-hdl:`util_dacfifo `) which will +cyclically stream the samples at the ``tx_device_clk`` data rate. The space +allocated in the transmit buffer for each channel depends on the number +of currently active channels. It goes up to M x 64k samples if a single +channel is selected or 64k samples per channel if all channels are +selected. + +All cores from the receive and transmit chains are programmable through +an AXI-Lite interface. + +The transmit and receive chains can operate at different data rates +having separate ``rx_device_clk``/``tx_device_clk`` and corresponding lane rates +but must share the same reference clock. + Supported boards ------------------------------------------------------------------------------- +- :adi:`AD9084-EBZ ` evaluation board + Supported devices ------------------------------------------------------------------------------- +- :adi:`AD9084` + Supported carriers ------------------------------------------------------------------------------- +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 1 + + * - Evaluation board + - Carrier + - FMC slot + - Maximum number of lanes + * - :adi:`AD9084-EBZ ` + - :intel:`FM87 ` + - FMCB + - 16 (8 per Apollo side) + * - + - :xilinx:`VCU118` + - FMC+ + - 24 (12 per Apollo side) + * - + - :xilinx:`VCU128` + - FMC+ + - 24 (12 per Apollo side) + * - + - :xilinx:`VCK190` + - FMC2 + - 8 (4 per Apollo side) + * - + - :xilinx:`VPK180` + - FMC+ + - 8 (4 per Apollo side) + Block design ------------------------------------------------------------------------------- +.. important:: + + The Apollo chip is split into two sides, each side having up to 12 JESD lanes and 4 converters: + + - Side A + - Side B + + The ``ASYMMETRIC_A_B_MODE`` parameter is used to enable the asymmetric A/B mode + where each Apollo side has a separate JESD link inside the block design. + + If the ASYMMETRIC_A_B_MODE parameter is set to 0, the block design will merge + the two sides into a single link. + + Given the following JESD204 configuration and assuming that **ASYMMETRIC_A_B_MODE = 0**: + + - L = 8 + - M = 4 + - S = 1 + - N = NP = 16 + - **NUM_LINKS = 2** + + The resulted design will configure each Apollo side with the following + parameters, but will merge the two sides into a single JESD link inside the + design: + + - L = 8 + - M = 4 + - S = 1 + - N = NP = 16 + + If however, **NUM_LINKS = 1**, the design will configure each side with the + following parameters: + + - L = 4 + - M = 2 + - S = 1 + - N = NP = 16 + + Given the following JESD204 configuration and assuming that + **ASYMMETRIC_A_B_MODE = 1**: + + - L = 8 + - M = 4 + - S = 1 + - N = NP = 16 + - **NUM_LINKS is ignored** + + The resulted design will configure each Apollo side with the following + parameters, each having it's own JESD link inside the design: + + - L = 8 + - M = 4 + - S = 1 + - N = NP = 16 Block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The data path and clock domains are depicted in the below diagrams: + +Example block design for ASYMMETRIC_A_B_MODE=0; M=4; L=8; NUM_LINKS=2; JESD204C +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ad9084_204c_M4L8.svg + :width: 800 + :align: center + :alt: AD9084-FMC JESD204C ASYMMETRIC_A_B_MODE=0 M=4 L=8 NUM_LINKS=2 block diagram + +.. warning:: + + **Build instructions:** + + The project must be built with the following parameters: + + .. shell:: bash + :no-path: + + $make JESD_MODE=64B66B \ + $ RX_LANE_RATE=20.625 \ + $ TX_LANE_RATE=20.625 \ + $ RX_JESD_M=4 \ + $ RX_JESD_L=8 \ + $ RX_JESD_S=1 \ + $ RX_JESD_NP=16 \ + $ RX_NUM_LINKS=2 \ + $ TX_JESD_M=4 \ + $ TX_JESD_L=8 \ + $ TX_JESD_S=1 \ + $ TX_JESD_NP=16 \ + $ TX_NUM_LINKS=2 \ + $ ASYMMETRIC_A_B_MODE=0 + +The Rx link is operating with the following parameters on each Apollo side: + +- Rx Deframer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Mode 47) +- Sample Rate: 2500 MSPS +- RX_DEVICE_CLK: 312.5 MHz (Lane Rate/66) +- REF_CLK: 625 MHz (Lane Rate/33) +- JESD204C Lane Rate: 20.625 Gbps +- QPLL1 + +The Tx link is operating with the following parameters: + +- Tx Framer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Mode 47) +- Sample Rate: 2500 MSPS +- Dual link: No +- TX_DEVICE_CLK: 312.5 MHz (Lane Rate/66) +- REF_CLK: 625 MHz (Lane Rate/33) +- JESD204C Lane Rate: 20.625 Gbps +- QPLL1 + +.. important:: + Because of the two Apollo sides, the total number of lanes in the design is 16 and the total number of converters is 8. + +Example block design for ASYMMETRIC_A_B_MODE=1; M=4; L=8; JESD204C +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ad9084_204c_M4L8_asymmetric.svg + :width: 800 + :align: center + :alt: AD9084-FMC JESD204C ASYMMETRIC_A_B_MODE=1 M=4 L=8 NUM_LINKS=2 block diagram + +.. warning:: + + **Build instructions:** + + The project must be built with the following parameters: + + .. shell:: bash + :no-path: + + $make JESD_MODE=64B66B \ + $ RX_LANE_RATE=20.625 \ + $ TX_LANE_RATE=20.625 \ + $ RX_JESD_M=4 \ + $ RX_JESD_L=8 \ + $ RX_JESD_S=1 \ + $ RX_JESD_NP=16 \ + $ TX_JESD_M=4 \ + $ TX_JESD_L=8 \ + $ TX_JESD_S=1 \ + $ TX_JESD_NP=16 \ + $ ASYMMETRIC_A_B_MODE=1 \ + $ RX_B_LANE_RATE=20.625 \ + $ TX_B_LANE_RATE=20.625 \ + $ RX_B_JESD_M=4 \ + $ RX_B_JESD_L=8 \ + $ RX_B_JESD_S=1 \ + $ RX_B_JESD_NP=16 \ + $ TX_B_JESD_M=4 \ + $ TX_B_JESD_L=8 \ + $ TX_B_JESD_S=1 \ + $ TX_B_JESD_NP=16 + + +The Rx link is operating with the following parameters on each Apollo side: + +- Rx Deframer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Mode 47) +- Sample Rate: 2500 MSPS +- RX_DEVICE_CLK: 312.5 MHz (Lane Rate/66) +- REF_CLK: 625 MHz (Lane Rate/33) +- JESD204C Lane Rate: 20.625 Gbps +- QPLL1 + +The Tx link is operating with the following parameters: + +- Tx Framer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Mode 47) +- Sample Rate: 2500 MSPS +- Dual link: No +- TX_DEVICE_CLK: 312.5 MHz (Lane Rate/66) +- REF_CLK: 625 MHz (Lane Rate/33) +- JESD204C Lane Rate: 20.625 Gbps +- QPLL1 + Configuration modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The block design supports configuration of parameters and scales. + +We have listed a couple of examples at section :ref:`ad9084_ebz build` and +the default modes for each project. + +.. note:: + + The parameters for Rx or Tx links can be changed from the + **system_project.tcl** file, located in + hdl/projects/ad9084_ebz/$CARRIER/system_project.tcl + +.. important:: + + For JESD204B: + + .. math:: + + Lane Rate = \frac{IQ Sample Rate * M * NP * \frac{10}{8}}{L} + + For JESD204C: + + .. math:: + + Lane Rate = \frac{IQ Sample Rate * M * NP * \frac{66}{64}}{L} + +The following are the parameters of this project that can be configured: + +- JESD_MODE: used link layer encoder mode + + - 64B66B - 64b66b link layer defined in JESD204C, uses ADI IP as Physical + Layer (except for Versal / Intel) + - 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical + Layer +- HSCI_ENABLE: enables the HSCI IP (Xilinx only) +- ASYMMETRIC_A_B_MODE: enables the asymmetric A/B mode where each Apollo side has a separate JESD link (Xilinx only) +- RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA) (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE) (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- REF_CLK_RATE: the rate of the reference clock (Versal and Intel only) +- DEVICE_CLK_RATE: the rate of the device clock (Intel only) +- [RX/TX]_JESD_M: number of converters per link (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- [RX/TX]_JESD_L: number of lanes per link (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- [RX/TX]_JESD_S: number of samples per frame (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- [RX/TX]_JESD_NP: number of bits per sample (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- [RX/TX]_NUM_LINKS: number of links (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in + kilosamples per converter (M) (A or A&B link if ASYMMETRIC_A_B_MODE = 0) +- RX_B_LANE_RATE: lane rate of the Rx link (MxFE to FPGA) (B link) +- TX_B_LANE_RATE: lane rate of the Tx link (FPGA to MxFE) (B link) +- [RX/TX]_B_JESD_M: number of converters per link (B link) +- [RX/TX]_B_JESD_L: number of lanes per link (B link) +- [RX/TX]_B_JESD_S: number of samples per frame (B link) +- [RX/TX]_B_JESD_NP: number of bits per sample (B link) +- [RX/TX]_B_NUM_LINKS: number of links (B link) +- [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in + kilosamples per converter (M) (B link) + Clock scheme ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The clock sources depend on the carrier that is used: + +:xilinx:`VCU118` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ad9084_clock_scheme_vcu118.svg + :width: 800 + :align: center + :alt: AD9084-EBZ VCU118 clock scheme + Limitations ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +.. warning:: + + For the parameter selection, the following restrictions apply: + + - NP = 8, 12, 16 + - F = 1, 2, 3, 4, 6, 8 + - :ref:`JESD204B/C Link Rx peripheral > restrictions ` + - :ref:`JESD204B/C Link Tx peripheral > restrictions ` + CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The addresses are dependent on the architecture of the FPGA, having an offset +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). + +Depending on the values of parameters $ASYMMETRIC_A_B_MODE, $ADI_PHY_SEL and $HSCI_ENABLE, +some IPs are instatiated and some are not. + +Check-out the table below to find out the conditions. + +========================= ========================================= =============== ============ +Instance Depends on parameter Microblaze ZynqMP +========================= ========================================= =============== ============ +apollo_rx_xcvr $ADI_PHY_SEL==1 0x44A6_0000 N/A +apollo_rx_jesd 0x44A9_0000 0xA4A9_0000 +rx_apollo_tpl_core 0x44A1_0000 0xA4A1_0000 +apollo_rx_dma 0x7C42_0000 0xBC42_0000 +apollo_rx_data_offload 0x7C45_0000 0xBC45_0000 +apollo_rx_b_xcvr $ADI_PHY_SEL==1 & $ASYMMETRIC_A_B_MODE==1 0x44AA_0000 N/A +apollo_rx_b_jesd $ASYMMETRIC_A_B_MODE==1 0x44AC_0000 0xA4AC_0000 +rx_b_apollo_tpl_core $ASYMMETRIC_A_B_MODE==1 0x44AB_0000 0xA4AB_0000 +apollo_rx_b_dma $ASYMMETRIC_A_B_MODE==1 0x7C47_0000 0xBC47_0000 +apollo_rx_b_data_offload $ASYMMETRIC_A_B_MODE==1 0x7C4A_0000 0xBC4A_0000 +apollo_tx_xcvr $ADI_PHY_SEL==1 0x44B6_0000 N/A +apollo_tx_jesd 0x44B9_0000 0xA4B9_0000 +tx_apollo_tpl_core 0x44B1_0000 0xA4B1_0000 +apollo_tx_dma 0x7C43_0000 0xBC43_0000 +apollo_tx_data_offload 0x7C44_0000 0xBC44_0000 +apollo_tx_b_xcvr $ADI_PHY_SEL==1 & $ASYMMETRIC_A_B_MODE==1 0x44BA_0000 N/A +apollo_tx_b_jesd $ASYMMETRIC_A_B_MODE==1 0x44BC_0000 0xA4BC_0000 +tx_b_apollo_tpl_core $ASYMMETRIC_A_B_MODE==1 0x44BB_0000 0xA4BB_0000 +apollo_tx_b_dma $ASYMMETRIC_A_B_MODE==1 0x7C48_0000 0xBC48_0000 +apollo_tx_b_data_offload $ASYMMETRIC_A_B_MODE==1 0x7C49_0000 0xBC44_0000 +axi_hsci $HSCI_ENABLE==1 0x7C50_0000 0xBC50_0000 +axi_hsci_clkgen $HSCI_ENABLE==1 0x44AD_0000 0xA4AD_0000 +axi_spi_2 0x44A8_0000 0xA4A8_0000 +========================= ========================================= =============== ============ + +For the Intel carriers, only a part of the CPU interrupts are specified, +as the rest depend on the values of $TX_NUM_OF_LANES +(see :git-hdl:`projects/ad9084_ebz/common/ad9084_ebz_qsys.tcl` +for more details). + +================================== =========== +Instance Intel +================================== =========== +apollo_rx_jesd204.link_reconfig 0x000C_0000 +apollo_rx_jesd204.link_management 0x000C_4000 +apollo_tx_jesd204.link_reconfig 0x000C_8000 +apollo_tx_jesd204.link_management 0x000C_C000 +apollo_rx_tpl.s_axi 0x000D_2000 +apollo_tx_tpl.s_axi 0x000D_4000 +apollo_rx_dma.s_axi 0x000D_8000 +apollo_tx_dma.s_axi 0x000D_C000 +apollo_gpio.s1 0x000E_0000 +apollo_spi.spi_control_port 0x000E_A000 +================================== =========== + SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 1 + + * - SPI type + - SPI manager instance + - SPI subordinate + - CS + * - PS + - spi0 + - ADF4382 + - 0 + * - PS + - spi0 + - HMC7044 + - 1 + * - PL + - axi_spi_2 + - AD9084 + - 0 + GPIOs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The following table lists the GPIO signals used in this project that +are connected to the Apollo evaluation board and are common between +all the carriers. + +.. list-table:: + :widths: 20 20 20 20 20 + :header-rows: 2 + + * - Apollo GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + - Software GPIO + * - + - (from FPGA view) + - + - Microblaze + - ZynqMP + * - resetb + - OUT + - 62 + - 62 + - 30 + * - trig_b[1:0] + - OUT + - 61:60 + - 61:60 + - 29:28 + * - trig_a[1:0] + - OUT + - 59:58 + - 59:58 + - 27:26 + * - trig_in + - IN + - 53 + - 53 + - 21 + * - aux_gpio + - INOUT + - 48 + - 48 + - 16 + * - gpio[30:15] + - INOUT + - 47:32 + - 47:32 + - 15:0 + +The following table lists the GPIO signals that are only present +in the Versal projects. + +They are used from the linux kernel to +control the reset sequence of the GTY/GTYP transceivers. + +.. list-table:: + :widths: 40 20 20 20 + :header-rows: 2 + + * - Versal transceivers GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + * - + - (from FPGA view) + - + - ZynqMP + * - tx_reset_datapath + - IN + - 71 + - 39 + * - rx_reset_datapath + - IN + - 70 + - 38 + * - tx_reset_pll_and_datapath + - IN + - 69 + - 37 + * - rx_reset_pll_and_datapath + - IN + - 68 + - 36 + * - gt_reset + - IN + - 67 + - 35 + * - mst_resetdone + - OUT + - 66 + - 34 + * - tx_resetdone + - OUT + - 65 + - 33 + * - rx_resetdone + - OUT + - 64 + - 32 + * - tx_b_reset_datapath + - IN + - 79 + - 47 + * - rx_b_reset_datapath + - IN + - 78 + - 46 + * - tx_b_reset_pll_and_datapath + - IN + - 77 + - 45 + * - rx_b_reset_pll_and_datapath + - IN + - 76 + - 44 + * - gt_b_reset + - IN + - 75 + - 43 + * - mst_b_resetdone + - OUT + - 74 + - 42 + * - tx_b_resetdone + - OUT + - 73 + - 41 + * - rx_b_resetdone + - OUT + - 72 + - 40 + +The following table lists the GPIOs that are only preset on the Intel +carriers. + +.. list-table:: + :widths: 40 20 20 20 + :header-rows: 2 + + * - Intel GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + * - + - (from FPGA view) + - + - ZynqMP + * - tx_fifo_bypass_bypass + - IN + - 63 + - 31 + Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Below are the Programmable Logic interrupts used in this project. + +==================== === ================ ============ +Instance name HDL Linux Microblaze Linux ZynqMP +==================== === ================ ============ +axi_apollo_rx_dma 13 13 97 +axi_apollo_tx_dma 12 12 96 +axi_apollo_rx_jesd 11 11 95 +axi_apollo_tx_jesd 10 10 94 +axi_spi_2 9 9 93 +axi_apollo_rx_b_dma 4 4 88 +axi_apollo_tx_b_dma 3 3 87 +axi_apollo_rx_b_jesd 2 2 86 +axi_apollo_tx_b_jesd 1 1 85 +==================== === ================ ============ + +.. _ad9084_ebz build: + Building the HDL project ------------------------------------------------------------------------------- +The design is built upon ADI's generic HDL reference design framework. +ADI distributes the bit/elf files of these projects as part of the +:dokuwiki:`ADI Kuiper Linux `. +If you want to build the sources, ADI makes them available on the +:git-hdl:`HDL repository `. To get the source you must +`clone `__ +the HDL repository. + +Then go to the :git-hdl:`projects/ad9084_ebz` +location and run the make command by typing in you command prompt: + +Example for building the project with parameters: + +**Linux/Cygwin/WSL** + +.. shell:: + :show-user: + + $cd hdl/projects/ad9084_ebz/vck190 + $make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 \ + $ RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 \ + $ RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 \ + $ TX_JESD_S=1 TX_JESD_NP=16 + +The following dropdowns contain tables with the parameters that can be used to +configure this project, depending on the carrier used. +Where a cell contains a --- (dash) it means that the parameter doesn't exist +for that project (ad9084_ebz/$carrier). + +.. warning:: + + For the parameter selection, the following restrictions apply: + + - NP = 8, 12, 16 + - F = 1, 2, 3, 4, 6, 8 + - :ref:`JESD204B/C Link Rx peripheral > restrictions ` + - :ref:`JESD204B/C Link Tx peripheral > restrictions ` + + ``NP`` notation is equivalent with ``N'`` + +.. collapsible:: Default values of the make parameters for AD9084-EBZ + + +---------------------+---------------------------------------------+ + | Parameter | Default value of the parameters | + | +--------+--------+---------+--------+--------+ + | | FM87 | VCU118 | VCU128 | VCK190 | VPK180 | + +=====================+========+========+=========+========+========+ + | JESD_MODE | 64B66B | 64B66B | 64B66B | 64B66B | 64B66B | + +---------------------+--------+--------+---------+--------+--------+ + | ENABLE_HSCI |:red:`-`| 1 | :red:`-`| 1* | 1* | + +---------------------+--------+--------+---------+--------+--------+ + | REF_CLK_RATE* | 312.5 | --- | --- | 312.5 | 312.5 | + +---------------------+--------+--------+---------+--------+--------+ + | DEVICE_CLK_RATE** | 312.5 | --- | --- | --- | --- | + +---------------------+--------+--------+---------+--------+--------+ + | RX_LANE_RATE | 20.625 | 20.625 | 10.3125 | 20.625 | 20.625 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_LANE_RATE | 20.625 | 20.625 | 10.3125 | 20.625 | 20.625 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_JESD_M | 4 | 4 | 4 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_JESD_L | 8 | 8 | 8 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_JESD_S | 1 | 1 | 1 | 1 | 1 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_JESD_NP | 16 | 16 | 16 | 16 | 16 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_NUM_LINKS | 2 | 1 | 1 | 2 | 2 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_JESD_M | 4 | 4 | 4 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_JESD_L | 8 | 8 | 8 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_JESD_S | 1 | 1 | 1 | 1 | 1 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_JESD_NP | 16 | 16 | 16 | 16 | 16 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_NUM_LINKS | 2 | 1 | 1 | 2 | 2 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_KS_PER_CHANNEL | 16 | 32 | 65536 | 64 | 64 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_KS_PER_CHANNEL | 16 | 32 | 65536 | 64 | 64 | + +---------------------+--------+--------+---------+--------+--------+ + | ASYMMETRIC_A_B_MODE |:red:`-`| 1 | 1 | 0 | 0 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_B_LANE_RATE |:red:`-`| 20.625 | 10.3125 | 20.625 | 20.625 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_B_LANE_RATE |:red:`-`| 20.625 | 10.3125 | 20.625 | 20.625 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_B_JESD_M |:red:`-`| 4 | 4 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_B_JESD_L |:red:`-`| 8 | 8 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_B_JESD_S |:red:`-`| 1 | 1 | 1 | 1 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_B_JESD_NP |:red:`-`| 16 | 16 | 16 | 16 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_B_JESD_M |:red:`-`| 4 | 4 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_B_JESD_L |:red:`-`| 8 | 8 | 4 | 4 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_B_JESD_S |:red:`-`| 1 | 1 | 1 | 1 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_B_JESD_NP |:red:`-`| 16 | 16 | 16 | 16 | + +---------------------+--------+--------+---------+--------+--------+ + | RX_B_KS_PER_CHANNEL |:red:`-`| 32 | 65536 | 64 | 64 | + +---------------------+--------+--------+---------+--------+--------+ + | TX_B_KS_PER_CHANNEL |:red:`-`| 32 | 65536 | 64 | 64 | + +---------------------+--------+--------+---------+--------+--------+ + | ADC_DO_MEM_TYPE | --- | --- | 2 | --- | --- | + +---------------------+--------+--------+---------+--------+--------+ + | DAC_DO_MEM_TYPE | --- | --- | 2 | --- | --- | + +---------------------+--------+--------+---------+--------+--------+ + + .. admonition:: Legend + :class: note + + :red:`-` --- this feature is not supported + + `*` --- can be disabled + +The result of the build, if parameters were used, will be in a folder named +by the configuration used: + +if the following command was run + +``make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16`` + +then the folder name will be: + +``RXRATE2_5_TXRATE2_5_RXL8_RXM4_RXS1_RXNP16_TXL8_TXM4_TXS1_TXNP16`` +because of truncation of some keywords so the name will not exceed the limits +of the Operating System (``JESD``, ``LANE``, etc. are removed) of 260 +characters. + +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. + Software considerations ------------------------------------------------------------------------------- +ADC - crossbar config +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Due to physical constraints, Rx lanes are reordered as described in the +following table. + +e.g physical lane 2 from ADC from A side connects to logical lane 1 +from the VCU118. Therefore the crossbar from the device must be set +accordingly. + +============== =============== =============== =============== =============== +ADC A phy Lane VCU118 VCU128 VCK190 / VPK180 FM87 +============== =============== =============== =============== =============== +0 7 11 5 11 +1 5 3 1 9 +2 1 8 3 8 +3 2 9 7 10 +4 11 7 N/C 7 +5 3 5 N/C 3 +6 8 1 N/C 1 +7 9 2 N/C 5 +8 10 10 N/C N/C +9 6 6 N/C N/C +10 4 4 N/C N/C +11 0 0 N/C N/C +============== =============== =============== =============== =============== + +============== =============== =============== =============== =============== +ADC B phy Lane VCU118 VCU128 VCK190 / VPK180 FM87 +============== =============== =============== =============== =============== +0 10 3 1 11 +1 6 2 7 9 +2 4 5 10 8 +3 0 7 3 5 +4 3 8 N/C 3 +5 2 1 N/C 10 +6 5 11 N/C 7 +7 7 9 N/C 1 +8 8 10 N/C N/C +9 1 6 N/C N/C +10 11 4 N/C N/C +11 9 0 N/C N/C +============== =============== =============== =============== =============== + +DAC - crossbar config +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Due to physical constraints, Tx lanes are reordered as described in the +following table. + +e.g physical lane 2 from DAC from A side connects to logical lane 9 +from the VCU118. Therefore the crossbar from the device must be set +accordingly. + +============== =============== =============== =============== =============== +DAC A phy Lane VCU118 VCU128 VCK190 / VPK180 FM87 +============== =============== =============== =============== =============== +0 10 5 11 2 +1 8 1 3 1 +2 9 3 8 5 +3 11 7 9 7 +4 5 10 N/C 9 +5 1 8 N/C 8 +6 3 9 N/C 3 +7 7 11 N/C 11 +8 4 4 N/C N/C +9 6 6 N/C N/C +10 2 2 N/C N/C +11 0 0 N/C N/C +============== =============== =============== =============== =============== + +============== =============== =============== =============== =============== +DAC B phy Lane VCU118 VCU128 VCK190 / VPK180 FM87 +============== =============== =============== =============== =============== +0 4 1 3 9 +1 6 7 2 11 +2 2 10 5 1 +3 0 3 7 8 +4 1 5 N/C 7 +5 7 8 N/C 5 +6 10 9 N/C 2 +7 3 11 N/C 3 +8 5 4 N/C N/C +9 8 6 N/C N/C +10 9 2 N/C N/C +11 11 0 N/C N/C +============== =============== =============== =============== =============== + +Resources +------------------------------------------------------------------------------- + +Systems related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :dokuwiki:`[Wiki] AD9084 Prototyping Platform User Guide ` +- Here you can find all the quick start guides on wiki documentation + :dokuwiki:`[Wiki] AD9084 Quick Start Guides ` + +Here you can find the quick start guides available for these evaluation boards: + +.. list-table:: + :widths: 20 20 40 20 + :header-rows: 1 + + * - Evaluation board + - Microblaze + - Versal + - Agilex 7 + * - AD9084 + - :dokuwiki:`VCU118 ` + - :dokuwiki:`VCK190/VMK180/VPK180 ` + - :dokuwiki:`FM87 ` + + Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +- Product datasheets: + + - :adi:`AD9084` + +.. + - :adi:`UG-1578, Device User Guide ` + - :adi:`UG-1829, Evaluation Board User Guide ` + HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +- :git-hdl:`ad9084_ebz HDL project source code ` + +.. list-table:: + :widths: 30 35 35 + :header-rows: 1 + + * - IP name + - Source code link + - Documentation link + * - AXI_DMAC + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` + * - AXI_SYSID + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` + * - SYSID_ROM + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` + * - UTIL_CPACK2 + - :git-hdl:`library/util_pack/util_cpack2` + - :ref:`util_cpack2` + * - UTIL_UPACK2 + - :git-hdl:`library/util_pack/util_upack2` + - :ref:`util_upack2` + * - UTIL_ADXCVR for AMD + - :git-hdl:`library/xilinx/util_adxcvr` + - :ref:`util_adxcvr` + * - AXI_ADXCVR for Intel + - :git-hdl:`library/intel/axi_adxcvr` + - :ref:`axi_adxcvr intel` + * - AXI_ADXCVR for AMD + - :git-hdl:`library/xilinx/axi_adxcvr` + - :ref:`axi_adxcvr amd` + * - AXI_JESD204_RX + - :git-hdl:`library/jesd204/axi_jesd204_rx` + - :ref:`axi_jesd204_rx` + * - AXI_JESD204_TX + - :git-hdl:`library/jesd204/axi_jesd204_tx` + - :ref:`axi_jesd204_tx` + * - JESD204_TPL_ADC + - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc` + - :ref:`ad_ip_jesd204_tpl_adc` + * - JESD204_TPL_DAC + - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` + - :ref:`ad_ip_jesd204_tpl_dac` + +- :dokuwiki:`[Wiki] Generic JESD204B block designs ` +- :ref:`jesd204` + Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +- :dokuwiki:`[Wiki] AD9084-EBZ Linux driver wiki page ` +- Python support: + + - `AD9084 class documentation `__ + - `PyADI-IIO documentation `__ + +.. include:: ../common/more_information.rst + +.. include:: ../common/support.rst diff --git a/docs/projects/ad9084_fmca_ebz/index.rst b/docs/projects/ad9084_fmca_ebz/index.rst deleted file mode 100644 index 7b45b7414fd..00000000000 --- a/docs/projects/ad9084_fmca_ebz/index.rst +++ /dev/null @@ -1,931 +0,0 @@ -.. _ad9084_fmca_ebz: - -AD9084 (Apollo) HDL project -=============================================================================== - -Overview -------------------------------------------------------------------------------- - -The :adi:`AD9084-FMCA-EBZ ` reference design -(also known as Apollo) is a processor based -(e.g. Microblaze) embedded system. -This reference design works with :adi:`EVAL-AD9084`. -The design consists from a receive and a transmit chain. - -The **receive chain** transports the captured samples from ADC to the system -memory (DDR). Before transferring the data to DDR, the samples are stored -in a buffer implemented on BRAMs from the FPGA fabric -(:git-hdl:`util_adcfifo `). -The space allocated in the buffer for each channel -depends on the number of currently active channels. It goes up to M x -64k samples if a single channel is selected or 64k samples per channel -if all channels are selected. - -The **transmit chain** transports samples from the system memory to the DAC -devices. Before streaming out the data to the DAC through the JESD link, -the samples first are loaded into a buffer -(:git-hdl:`util_dacfifo `) which will -cyclically stream the samples at the ``tx_device_clk`` data rate. The space -allocated in the transmit buffer for each channel depends on the number -of currently active channels. It goes up to M x 64k samples if a single -channel is selected or 64k samples per channel if all channels are -selected. - -All cores from the receive and transmit chains are programmable through -an AXI-Lite interface. - -The transmit and receive chains can operate at different data rates -having separate ``rx_device_clk``/``tx_device_clk`` and corresponding lane rates -but must share the same reference clock. - -Supported boards -------------------------------------------------------------------------------- - -- :adi:`AD9084-FMCA-EBZ ` evaluation board - -Supported devices -------------------------------------------------------------------------------- - -- :adi:`AD9084` - -Supported carriers -------------------------------------------------------------------------------- - -.. list-table:: - :widths: 25 25 25 25 - :header-rows: 1 - - * - Evaluation board - - Carrier - - FMC slot - - Maximum number of lanes - * - :adi:`AD9084-FMCA-EBZ ` - - :intel:`FM87 ` - - FMCB - - 16 (8 per Apollo side) - * - - - :xilinx:`VCU118` - - FMC+ - - 24 (12 per Apollo side) - * - - - :xilinx:`VCU128` - - FMC+ - - 24 (12 per Apollo side) - * - - - :xilinx:`VCK190` - - FMC2 - - 8 (4 per Apollo side) - * - - - :xilinx:`VPK180` - - FMC+ - - 8 (4 per Apollo side) - -Block design -------------------------------------------------------------------------------- -.. important:: - - The Apollo chip is split into two sides, each side having up to 12 JESD lanes and 4 converters: - - - Side A - - Side B - - The ``ASYMMETRIC_A_B_MODE`` parameter is used to enable the asymmetric A/B mode - where each Apollo side has a separate JESD link inside the block design. - - If the ASYMMETRIC_A_B_MODE parameter is set to 0, the block design will merge - the two sides into a single link. - - Given the following JESD204 configuration and assuming that **ASYMMETRIC_A_B_MODE = 0**: - - - L = 8 - - M = 4 - - S = 1 - - N = NP = 16 - - **NUM_LINKS = 2** - - The resulted design will configure each Apollo side with the following - parameters, but will merge the two sides into a single JESD link inside the - design: - - - L = 8 - - M = 4 - - S = 1 - - N = NP = 16 - - If however, **NUM_LINKS = 1**, the design will configure each side with the - following parameters: - - - L = 4 - - M = 2 - - S = 1 - - N = NP = 16 - - Given the following JESD204 configuration and assuming that - **ASYMMETRIC_A_B_MODE = 1**: - - - L = 8 - - M = 4 - - S = 1 - - N = NP = 16 - - **NUM_LINKS is ignored** - - The resulted design will configure each Apollo side with the following - parameters, each having it's own JESD link inside the design: - - - L = 8 - - M = 4 - - S = 1 - - N = NP = 16 - -Block diagram -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The data path and clock domains are depicted in the below diagrams: - -Example block design for ASYMMETRIC_A_B_MODE=0; M=4; L=8; NUM_LINKS=2; JESD204C -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. image:: ad9084_204c_M4L8.svg - :width: 800 - :align: center - :alt: AD9084-FMC JESD204C ASYMMETRIC_A_B_MODE=0 M=4 L=8 NUM_LINKS=2 block diagram - -.. warning:: - - **Build instructions:** - - The project must be built with the following parameters: - - .. shell:: bash - :no-path: - - $make JESD_MODE=64B66B \ - $ RX_LANE_RATE=20.625 \ - $ TX_LANE_RATE=20.625 \ - $ RX_JESD_M=4 \ - $ RX_JESD_L=8 \ - $ RX_JESD_S=1 \ - $ RX_JESD_NP=16 \ - $ RX_NUM_LINKS=2 \ - $ TX_JESD_M=4 \ - $ TX_JESD_L=8 \ - $ TX_JESD_S=1 \ - $ TX_JESD_NP=16 \ - $ TX_NUM_LINKS=2 \ - $ ASYMMETRIC_A_B_MODE=0 - -The Rx link is operating with the following parameters on each Apollo side: - -- Rx Deframer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Mode 47) -- Sample Rate: 2500 MSPS -- RX_DEVICE_CLK: 312.5 MHz (Lane Rate/66) -- REF_CLK: 625 MHz (Lane Rate/33) -- JESD204C Lane Rate: 20.625 Gbps -- QPLL1 - -The Tx link is operating with the following parameters: - -- Tx Framer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Mode 47) -- Sample Rate: 2500 MSPS -- Dual link: No -- TX_DEVICE_CLK: 312.5 MHz (Lane Rate/66) -- REF_CLK: 625 MHz (Lane Rate/33) -- JESD204C Lane Rate: 20.625 Gbps -- QPLL1 - -.. important:: - Because of the two Apollo sides, the total number of lanes in the design is 16 and the total number of converters is 8. - -Example block design for ASYMMETRIC_A_B_MODE=1; M=4; L=8; JESD204C -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. image:: ad9084_204c_M4L8_asymmetric.svg - :width: 800 - :align: center - :alt: AD9084-FMC JESD204C ASYMMETRIC_A_B_MODE=1 M=4 L=8 NUM_LINKS=2 block diagram - -.. warning:: - - **Build instructions:** - - The project must be built with the following parameters: - - .. shell:: bash - :no-path: - - $make JESD_MODE=64B66B \ - $ RX_LANE_RATE=20.625 \ - $ TX_LANE_RATE=20.625 \ - $ RX_JESD_M=4 \ - $ RX_JESD_L=8 \ - $ RX_JESD_S=1 \ - $ RX_JESD_NP=16 \ - $ TX_JESD_M=4 \ - $ TX_JESD_L=8 \ - $ TX_JESD_S=1 \ - $ TX_JESD_NP=16 \ - $ ASYMMETRIC_A_B_MODE=1 \ - $ RX_B_LANE_RATE=20.625 \ - $ TX_B_LANE_RATE=20.625 \ - $ RX_B_JESD_M=4 \ - $ RX_B_JESD_L=8 \ - $ RX_B_JESD_S=1 \ - $ RX_B_JESD_NP=16 \ - $ TX_B_JESD_M=4 \ - $ TX_B_JESD_L=8 \ - $ TX_B_JESD_S=1 \ - $ TX_B_JESD_NP=16 - - -The Rx link is operating with the following parameters on each Apollo side: - -- Rx Deframer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Mode 47) -- Sample Rate: 2500 MSPS -- RX_DEVICE_CLK: 312.5 MHz (Lane Rate/66) -- REF_CLK: 625 MHz (Lane Rate/33) -- JESD204C Lane Rate: 20.625 Gbps -- QPLL1 - -The Tx link is operating with the following parameters: - -- Tx Framer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Mode 47) -- Sample Rate: 2500 MSPS -- Dual link: No -- TX_DEVICE_CLK: 312.5 MHz (Lane Rate/66) -- REF_CLK: 625 MHz (Lane Rate/33) -- JESD204C Lane Rate: 20.625 Gbps -- QPLL1 - -Configuration modes -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The block design supports configuration of parameters and scales. - -We have listed a couple of examples at section :ref:`ad9084_fmca_ebz build` and -the default modes for each project. - -.. note:: - - The parameters for Rx or Tx links can be changed from the - **system_project.tcl** file, located in - hdl/projects/ad9084_fmca_ebz/$CARRIER/system_project.tcl - -.. important:: - - For JESD204B: - - .. math:: - - Lane Rate = \frac{IQ Sample Rate * M * NP * \frac{10}{8}}{L} - - For JESD204C: - - .. math:: - - Lane Rate = \frac{IQ Sample Rate * M * NP * \frac{66}{64}}{L} - -The following are the parameters of this project that can be configured: - -- JESD_MODE: used link layer encoder mode - - - 64B66B - 64b66b link layer defined in JESD204C, uses ADI IP as Physical - Layer (except for Versal / Intel) - - 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical - Layer -- HSCI_ENABLE: enables the HSCI IP (Xilinx only) -- ASYMMETRIC_A_B_MODE: enables the asymmetric A/B mode where each Apollo side has a separate JESD link (Xilinx only) -- RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA) (A or A&B link if ASYMMETRIC_A_B_MODE = 0) -- TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE) (A or A&B link if ASYMMETRIC_A_B_MODE = 0) -- REF_CLK_RATE: the rate of the reference clock (Versal and Intel only) -- DEVICE_CLK_RATE: the rate of the device clock (Intel only) -- [RX/TX]_JESD_M: number of converters per link (A or A&B link if ASYMMETRIC_A_B_MODE = 0) -- [RX/TX]_JESD_L: number of lanes per link (A or A&B link if ASYMMETRIC_A_B_MODE = 0) -- [RX/TX]_JESD_S: number of samples per frame (A or A&B link if ASYMMETRIC_A_B_MODE = 0) -- [RX/TX]_JESD_NP: number of bits per sample (A or A&B link if ASYMMETRIC_A_B_MODE = 0) -- [RX/TX]_NUM_LINKS: number of links (A or A&B link if ASYMMETRIC_A_B_MODE = 0) -- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in - kilosamples per converter (M) (A or A&B link if ASYMMETRIC_A_B_MODE = 0) -- RX_B_LANE_RATE: lane rate of the Rx link (MxFE to FPGA) (B link) -- TX_B_LANE_RATE: lane rate of the Tx link (FPGA to MxFE) (B link) -- [RX/TX]_B_JESD_M: number of converters per link (B link) -- [RX/TX]_B_JESD_L: number of lanes per link (B link) -- [RX/TX]_B_JESD_S: number of samples per frame (B link) -- [RX/TX]_B_JESD_NP: number of bits per sample (B link) -- [RX/TX]_B_NUM_LINKS: number of links (B link) -- [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in - kilosamples per converter (M) (B link) - -Clock scheme -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The clock sources depend on the carrier that is used: - -:xilinx:`VCU118` -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. image:: ad9084_clock_scheme_vcu118.svg - :width: 800 - :align: center - :alt: AD9084-FMCA-EBZ VCU118 clock scheme - -Limitations -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. warning:: - - For the parameter selection, the following restrictions apply: - - - NP = 8, 12, 16 - - F = 1, 2, 3, 4, 6, 8 - - :ref:`JESD204B/C Link Rx peripheral > restrictions ` - - :ref:`JESD204B/C Link Tx peripheral > restrictions ` - -CPU/Memory interconnects addresses -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). - -Depending on the values of parameters $ASYMMETRIC_A_B_MODE, $ADI_PHY_SEL and $HSCI_ENABLE, -some IPs are instatiated and some are not. - -Check-out the table below to find out the conditions. - -========================= ========================================= =============== ============ -Instance Depends on parameter Microblaze ZynqMP -========================= ========================================= =============== ============ -apollo_rx_xcvr $ADI_PHY_SEL==1 0x44A6_0000 N/A -apollo_rx_jesd 0x44A9_0000 0xA4A9_0000 -rx_apollo_tpl_core 0x44A1_0000 0xA4A1_0000 -apollo_rx_dma 0x7C42_0000 0xBC42_0000 -apollo_rx_data_offload 0x7C45_0000 0xBC45_0000 -apollo_rx_b_xcvr $ADI_PHY_SEL==1 & $ASYMMETRIC_A_B_MODE==1 0x44AA_0000 N/A -apollo_rx_b_jesd $ASYMMETRIC_A_B_MODE==1 0x44AC_0000 0xA4AC_0000 -rx_b_apollo_tpl_core $ASYMMETRIC_A_B_MODE==1 0x44AB_0000 0xA4AB_0000 -apollo_rx_b_dma $ASYMMETRIC_A_B_MODE==1 0x7C47_0000 0xBC47_0000 -apollo_rx_b_data_offload $ASYMMETRIC_A_B_MODE==1 0x7C4A_0000 0xBC4A_0000 -apollo_tx_xcvr $ADI_PHY_SEL==1 0x44B6_0000 N/A -apollo_tx_jesd 0x44B9_0000 0xA4B9_0000 -tx_apollo_tpl_core 0x44B1_0000 0xA4B1_0000 -apollo_tx_dma 0x7C43_0000 0xBC43_0000 -apollo_tx_data_offload 0x7C44_0000 0xBC44_0000 -apollo_tx_b_xcvr $ADI_PHY_SEL==1 & $ASYMMETRIC_A_B_MODE==1 0x44BA_0000 N/A -apollo_tx_b_jesd $ASYMMETRIC_A_B_MODE==1 0x44BC_0000 0xA4BC_0000 -tx_b_apollo_tpl_core $ASYMMETRIC_A_B_MODE==1 0x44BB_0000 0xA4BB_0000 -apollo_tx_b_dma $ASYMMETRIC_A_B_MODE==1 0x7C48_0000 0xBC48_0000 -apollo_tx_b_data_offload $ASYMMETRIC_A_B_MODE==1 0x7C49_0000 0xBC44_0000 -axi_hsci $HSCI_ENABLE==1 0x7C50_0000 0xBC50_0000 -axi_hsci_clkgen $HSCI_ENABLE==1 0x44AD_0000 0xA4AD_0000 -axi_spi_2 0x44A8_0000 0xA4A8_0000 -========================= ========================================= =============== ============ - -For the Intel carriers, only a part of the CPU interrupts are specified, -as the rest depend on the values of $TX_NUM_OF_LANES -(see :git-hdl:`projects/ad9084_fmca_ebz/common/ad9084_fmca_ebz_qsys.tcl` -for more details). - -================================== =========== -Instance Intel -================================== =========== -apollo_rx_jesd204.link_reconfig 0x000C_0000 -apollo_rx_jesd204.link_management 0x000C_4000 -apollo_tx_jesd204.link_reconfig 0x000C_8000 -apollo_tx_jesd204.link_management 0x000C_C000 -apollo_rx_tpl.s_axi 0x000D_2000 -apollo_tx_tpl.s_axi 0x000D_4000 -apollo_rx_dma.s_axi 0x000D_8000 -apollo_tx_dma.s_axi 0x000D_C000 -apollo_gpio.s1 0x000E_0000 -apollo_spi.spi_control_port 0x000E_A000 -================================== =========== - -SPI connections -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. list-table:: - :widths: 25 25 25 25 - :header-rows: 1 - - * - SPI type - - SPI manager instance - - SPI subordinate - - CS - * - PS - - spi0 - - ADF4382 - - 0 - * - PS - - spi0 - - HMC7044 - - 1 - * - PL - - axi_spi_2 - - AD9084 - - 0 - -GPIOs -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The following table lists the GPIO signals used in this project that -are connected to the Apollo evaluation board and are common between -all the carriers. - -.. list-table:: - :widths: 20 20 20 20 20 - :header-rows: 2 - - * - Apollo GPIO signal - - Direction - - HDL GPIO EMIO - - Software GPIO - - Software GPIO - * - - - (from FPGA view) - - - - Microblaze - - ZynqMP - * - resetb - - OUT - - 62 - - 62 - - 30 - * - trig_b[1:0] - - OUT - - 61:60 - - 61:60 - - 29:28 - * - trig_a[1:0] - - OUT - - 59:58 - - 59:58 - - 27:26 - * - trig_in - - IN - - 53 - - 53 - - 21 - * - aux_gpio - - INOUT - - 48 - - 48 - - 16 - * - gpio[30:15] - - INOUT - - 47:32 - - 47:32 - - 15:0 - -The following table lists the GPIO signals that are only present -in the Versal projects. - -They are used from the linux kernel to -control the reset sequence of the GTY/GTYP transceivers. - -.. list-table:: - :widths: 40 20 20 20 - :header-rows: 2 - - * - Versal transceivers GPIO signal - - Direction - - HDL GPIO EMIO - - Software GPIO - * - - - (from FPGA view) - - - - ZynqMP - * - tx_reset_datapath - - IN - - 71 - - 39 - * - rx_reset_datapath - - IN - - 70 - - 38 - * - tx_reset_pll_and_datapath - - IN - - 69 - - 37 - * - rx_reset_pll_and_datapath - - IN - - 68 - - 36 - * - gt_reset - - IN - - 67 - - 35 - * - mst_resetdone - - OUT - - 66 - - 34 - * - tx_resetdone - - OUT - - 65 - - 33 - * - rx_resetdone - - OUT - - 64 - - 32 - * - tx_b_reset_datapath - - IN - - 79 - - 47 - * - rx_b_reset_datapath - - IN - - 78 - - 46 - * - tx_b_reset_pll_and_datapath - - IN - - 77 - - 45 - * - rx_b_reset_pll_and_datapath - - IN - - 76 - - 44 - * - gt_b_reset - - IN - - 75 - - 43 - * - mst_b_resetdone - - OUT - - 74 - - 42 - * - tx_b_resetdone - - OUT - - 73 - - 41 - * - rx_b_resetdone - - OUT - - 72 - - 40 - -The following table lists the GPIOs that are only preset on the Intel -carriers. - -.. list-table:: - :widths: 40 20 20 20 - :header-rows: 2 - - * - Intel GPIO signal - - Direction - - HDL GPIO EMIO - - Software GPIO - * - - - (from FPGA view) - - - - ZynqMP - * - tx_fifo_bypass_bypass - - IN - - 63 - - 31 - -Interrupts -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Below are the Programmable Logic interrupts used in this project. - -==================== === ================ ============ -Instance name HDL Linux Microblaze Linux ZynqMP -==================== === ================ ============ -axi_apollo_rx_dma 13 13 97 -axi_apollo_tx_dma 12 12 96 -axi_apollo_rx_jesd 11 11 95 -axi_apollo_tx_jesd 10 10 94 -axi_spi_2 9 9 93 -axi_apollo_rx_b_dma 4 4 88 -axi_apollo_tx_b_dma 3 3 87 -axi_apollo_rx_b_jesd 2 2 86 -axi_apollo_tx_b_jesd 1 1 85 -==================== === ================ ============ - -.. _ad9084_fmca_ebz build: - -Building the HDL project -------------------------------------------------------------------------------- - -The design is built upon ADI's generic HDL reference design framework. -ADI distributes the bit/elf files of these projects as part of the -:dokuwiki:`ADI Kuiper Linux `. -If you want to build the sources, ADI makes them available on the -:git-hdl:`HDL repository `. To get the source you must -`clone `__ -the HDL repository. - -Then go to the :git-hdl:`projects/ad9084_fmca_ebz` -location and run the make command by typing in you command prompt: - -Example for building the project with parameters: - -**Linux/Cygwin/WSL** - -.. shell:: - :show-user: - - $cd hdl/projects/ad9084_fmca_ebz/vck190 - $make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 \ - $ RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 \ - $ RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 \ - $ TX_JESD_S=1 TX_JESD_NP=16 - -The following dropdowns contain tables with the parameters that can be used to -configure this project, depending on the carrier used. -Where a cell contains a --- (dash) it means that the parameter doesn't exist -for that project (ad9084_fmca_ebz/$carrier). - -.. warning:: - - For the parameter selection, the following restrictions apply: - - - NP = 8, 12, 16 - - F = 1, 2, 3, 4, 6, 8 - - :ref:`JESD204B/C Link Rx peripheral > restrictions ` - - :ref:`JESD204B/C Link Tx peripheral > restrictions ` - - ``NP`` notation is equivalent with ``N'`` - -.. collapsible:: Default values of the make parameters for AD9084-FMCA-EBZ - - +---------------------+---------------------------------------------+ - | Parameter | Default value of the parameters | - | +--------+--------+---------+--------+--------+ - | | FM87 | VCU118 | VCU128 | VCK190 | VPK180 | - +=====================+========+========+=========+========+========+ - | JESD_MODE | 64B66B | 64B66B | 64B66B | 64B66B | 64B66B | - +---------------------+--------+--------+---------+--------+--------+ - | ENABLE_HSCI |:red:`-`| 1 | :red:`-`| 1* | 1* | - +---------------------+--------+--------+---------+--------+--------+ - | REF_CLK_RATE* | 312.5 | --- | --- | 312.5 | 312.5 | - +---------------------+--------+--------+---------+--------+--------+ - | DEVICE_CLK_RATE** | 312.5 | --- | --- | --- | --- | - +---------------------+--------+--------+---------+--------+--------+ - | RX_LANE_RATE | 20.625 | 20.625 | 10.3125 | 20.625 | 20.625 | - +---------------------+--------+--------+---------+--------+--------+ - | TX_LANE_RATE | 20.625 | 20.625 | 10.3125 | 20.625 | 20.625 | - +---------------------+--------+--------+---------+--------+--------+ - | RX_JESD_M | 4 | 4 | 4 | 4 | 4 | - +---------------------+--------+--------+---------+--------+--------+ - | RX_JESD_L | 8 | 8 | 8 | 4 | 4 | - +---------------------+--------+--------+---------+--------+--------+ - | RX_JESD_S | 1 | 1 | 1 | 1 | 1 | - +---------------------+--------+--------+---------+--------+--------+ - | RX_JESD_NP | 16 | 16 | 16 | 16 | 16 | - +---------------------+--------+--------+---------+--------+--------+ - | RX_NUM_LINKS | 2 | 1 | 1 | 2 | 2 | - +---------------------+--------+--------+---------+--------+--------+ - | TX_JESD_M | 4 | 4 | 4 | 4 | 4 | - +---------------------+--------+--------+---------+--------+--------+ - | TX_JESD_L | 8 | 8 | 8 | 4 | 4 | - +---------------------+--------+--------+---------+--------+--------+ - | TX_JESD_S | 1 | 1 | 1 | 1 | 1 | - +---------------------+--------+--------+---------+--------+--------+ - | TX_JESD_NP | 16 | 16 | 16 | 16 | 16 | - +---------------------+--------+--------+---------+--------+--------+ - | TX_NUM_LINKS | 2 | 1 | 1 | 2 | 2 | - +---------------------+--------+--------+---------+--------+--------+ - | RX_KS_PER_CHANNEL | 16 | 32 | 65536 | 64 | 64 | - +---------------------+--------+--------+---------+--------+--------+ - | TX_KS_PER_CHANNEL | 16 | 32 | 65536 | 64 | 64 | - +---------------------+--------+--------+---------+--------+--------+ - | ASYMMETRIC_A_B_MODE |:red:`-`| 1 | 1 | 0 | 0 | - +---------------------+--------+--------+---------+--------+--------+ - | RX_B_LANE_RATE |:red:`-`| 20.625 | 10.3125 | 20.625 | 20.625 | - +---------------------+--------+--------+---------+--------+--------+ - | TX_B_LANE_RATE |:red:`-`| 20.625 | 10.3125 | 20.625 | 20.625 | - +---------------------+--------+--------+---------+--------+--------+ - | RX_B_JESD_M |:red:`-`| 4 | 4 | 4 | 4 | - +---------------------+--------+--------+---------+--------+--------+ - | RX_B_JESD_L |:red:`-`| 8 | 8 | 4 | 4 | - +---------------------+--------+--------+---------+--------+--------+ - | RX_B_JESD_S |:red:`-`| 1 | 1 | 1 | 1 | - +---------------------+--------+--------+---------+--------+--------+ - | RX_B_JESD_NP |:red:`-`| 16 | 16 | 16 | 16 | - +---------------------+--------+--------+---------+--------+--------+ - | TX_B_JESD_M |:red:`-`| 4 | 4 | 4 | 4 | - +---------------------+--------+--------+---------+--------+--------+ - | TX_B_JESD_L |:red:`-`| 8 | 8 | 4 | 4 | - +---------------------+--------+--------+---------+--------+--------+ - | TX_B_JESD_S |:red:`-`| 1 | 1 | 1 | 1 | - +---------------------+--------+--------+---------+--------+--------+ - | TX_B_JESD_NP |:red:`-`| 16 | 16 | 16 | 16 | - +---------------------+--------+--------+---------+--------+--------+ - | RX_B_KS_PER_CHANNEL |:red:`-`| 32 | 65536 | 64 | 64 | - +---------------------+--------+--------+---------+--------+--------+ - | TX_B_KS_PER_CHANNEL |:red:`-`| 32 | 65536 | 64 | 64 | - +---------------------+--------+--------+---------+--------+--------+ - | ADC_DO_MEM_TYPE | --- | --- | 2 | --- | --- | - +---------------------+--------+--------+---------+--------+--------+ - | DAC_DO_MEM_TYPE | --- | --- | 2 | --- | --- | - +---------------------+--------+--------+---------+--------+--------+ - - .. admonition:: Legend - :class: note - - :red:`-` --- this feature is not supported - - `*` --- can be disabled - -The result of the build, if parameters were used, will be in a folder named -by the configuration used: - -if the following command was run - -``make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16`` - -then the folder name will be: - -``RXRATE2_5_TXRATE2_5_RXL8_RXM4_RXS1_RXNP16_TXL8_TXM4_TXS1_TXNP16`` -because of truncation of some keywords so the name will not exceed the limits -of the Operating System (``JESD``, ``LANE``, etc. are removed) of 260 -characters. - -A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. - -Software considerations -------------------------------------------------------------------------------- - -ADC - crossbar config -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Due to physical constraints, Rx lanes are reordered as described in the -following table. - -e.g physical lane 2 from ADC from A side connects to logical lane 1 -from the VCU118. Therefore the crossbar from the device must be set -accordingly. - -============== =============== =============== =============== =============== -ADC A phy Lane VCU118 VCU128 VCK190 / VPK180 FM87 -============== =============== =============== =============== =============== -0 7 11 5 11 -1 5 3 1 9 -2 1 8 3 8 -3 2 9 7 10 -4 11 7 N/C 7 -5 3 5 N/C 3 -6 8 1 N/C 1 -7 9 2 N/C 5 -8 10 10 N/C N/C -9 6 6 N/C N/C -10 4 4 N/C N/C -11 0 0 N/C N/C -============== =============== =============== =============== =============== - -============== =============== =============== =============== =============== -ADC B phy Lane VCU118 VCU128 VCK190 / VPK180 FM87 -============== =============== =============== =============== =============== -0 10 3 1 11 -1 6 2 7 9 -2 4 5 10 8 -3 0 7 3 5 -4 3 8 N/C 3 -5 2 1 N/C 10 -6 5 11 N/C 7 -7 7 9 N/C 1 -8 8 10 N/C N/C -9 1 6 N/C N/C -10 11 4 N/C N/C -11 9 0 N/C N/C -============== =============== =============== =============== =============== - -DAC - crossbar config -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Due to physical constraints, Tx lanes are reordered as described in the -following table. - -e.g physical lane 2 from DAC from A side connects to logical lane 9 -from the VCU118. Therefore the crossbar from the device must be set -accordingly. - -============== =============== =============== =============== =============== -DAC A phy Lane VCU118 VCU128 VCK190 / VPK180 FM87 -============== =============== =============== =============== =============== -0 10 5 11 2 -1 8 1 3 1 -2 9 3 8 5 -3 11 7 9 7 -4 5 10 N/C 9 -5 1 8 N/C 8 -6 3 9 N/C 3 -7 7 11 N/C 11 -8 4 4 N/C N/C -9 6 6 N/C N/C -10 2 2 N/C N/C -11 0 0 N/C N/C -============== =============== =============== =============== =============== - -============== =============== =============== =============== =============== -DAC B phy Lane VCU118 VCU128 VCK190 / VPK180 FM87 -============== =============== =============== =============== =============== -0 4 1 3 9 -1 6 7 2 11 -2 2 10 5 1 -3 0 3 7 8 -4 1 5 N/C 7 -5 7 8 N/C 5 -6 10 9 N/C 2 -7 3 11 N/C 3 -8 5 4 N/C N/C -9 8 6 N/C N/C -10 9 2 N/C N/C -11 11 0 N/C N/C -============== =============== =============== =============== =============== - -Resources -------------------------------------------------------------------------------- - -Systems related -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -- :dokuwiki:`[Wiki] AD9084 Prototyping Platform User Guide ` -- Here you can find all the quick start guides on wiki documentation - :dokuwiki:`[Wiki] AD9084 Quick Start Guides ` - -Here you can find the quick start guides available for these evaluation boards: - -.. list-table:: - :widths: 20 20 40 20 - :header-rows: 1 - - * - Evaluation board - - Microblaze - - Versal - - Agilex 7 - * - AD9084 - - :dokuwiki:`VCU118 ` - - :dokuwiki:`VCK190/VMK180/VPK180 ` - - :dokuwiki:`FM87 ` - - -Hardware related -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -- Product datasheets: - - - :adi:`AD9084` -- `UG-1578, Device User Guide `__ -- `UG-1829, Evaluation Board User Guide `__ - -HDL related -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -- :git-hdl:`ad9084_fmca_ebz HDL project source code ` - -.. list-table:: - :widths: 30 35 35 - :header-rows: 1 - - * - IP name - - Source code link - - Documentation link - * - AXI_DMAC - - :git-hdl:`library/axi_dmac` - - :ref:`axi_dmac` - * - AXI_SYSID - - :git-hdl:`library/axi_sysid` - - :ref:`axi_sysid` - * - SYSID_ROM - - :git-hdl:`library/sysid_rom` - - :ref:`axi_sysid` - * - UTIL_CPACK2 - - :git-hdl:`library/util_pack/util_cpack2` - - :ref:`util_cpack2` - * - UTIL_UPACK2 - - :git-hdl:`library/util_pack/util_upack2` - - :ref:`util_upack2` - * - UTIL_ADXCVR for AMD - - :git-hdl:`library/xilinx/util_adxcvr` - - :ref:`util_adxcvr` - * - AXI_ADXCVR for Intel - - :git-hdl:`library/intel/axi_adxcvr` - - :ref:`axi_adxcvr intel` - * - AXI_ADXCVR for AMD - - :git-hdl:`library/xilinx/axi_adxcvr` - - :ref:`axi_adxcvr amd` - * - AXI_JESD204_RX - - :git-hdl:`library/jesd204/axi_jesd204_rx` - - :ref:`axi_jesd204_rx` - * - AXI_JESD204_TX - - :git-hdl:`library/jesd204/axi_jesd204_tx` - - :ref:`axi_jesd204_tx` - * - JESD204_TPL_ADC - - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc` - - :ref:`ad_ip_jesd204_tpl_adc` - * - JESD204_TPL_DAC - - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` - - :ref:`ad_ip_jesd204_tpl_dac` - -- :dokuwiki:`[Wiki] Generic JESD204B block designs ` -- :ref:`jesd204` - -Software related -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -- :dokuwiki:`[Wiki] AD9084-FMCA-EBZ Linux driver wiki page ` -- Python support: - - - `AD9084 class documentation `__ - - `PyADI-IIO documentation `__ - -.. include:: ../common/more_information.rst - -.. include:: ../common/support.rst diff --git a/docs/projects/index.rst b/docs/projects/index.rst index 061be415522..86caa2d8b57 100644 --- a/docs/projects/index.rst +++ b/docs/projects/index.rst @@ -51,7 +51,6 @@ Contents AD9081-FMCA-EBZ-X-BAND AD9083-EVB AD9084-EBZ - AD9084-FMCA-EBZ AD916x-FMC AD9208-DUAL-EBZ AD9209-FMCA-EBZ From 5db7ef9ee3e0be0dbbb35294eaa6307382c5f441 Mon Sep 17 00:00:00 2001 From: bluncan Date: Fri, 12 Sep 2025 10:38:42 +0300 Subject: [PATCH 5/5] docs: projects: ad9084_ebz: Remove VCU128 support and small fixes Signed-off-by: bluncan --- .../ad9084_ebz/ad9084_clock_scheme_vcu118.svg | 10 +- docs/projects/ad9084_ebz/index.rst | 415 +++++++++--------- 2 files changed, 217 insertions(+), 208 deletions(-) diff --git a/docs/projects/ad9084_ebz/ad9084_clock_scheme_vcu118.svg b/docs/projects/ad9084_ebz/ad9084_clock_scheme_vcu118.svg index fd64fbaa6be..7ebe6e6a136 100644 --- a/docs/projects/ad9084_ebz/ad9084_clock_scheme_vcu118.svg +++ b/docs/projects/ad9084_ebz/ad9084_clock_scheme_vcu118.svg @@ -1823,8 +1823,8 @@ inkscape:pageopacity="0.0" inkscape:pageshadow="2" inkscape:zoom="2.0000001" - inkscape:cx="501.99999" - inkscape:cy="203.49999" + inkscape:cx="500.49997" + inkscape:cy="323.49998" inkscape:document-units="mm" inkscape:current-layer="layer1" showgrid="false" @@ -1932,16 +1932,16 @@ inkscape:export-xdpi="96" xml:space="preserve" style="font-style:normal;font-weight:normal;font-size:5.58431px;line-height:0%;font-family:Arial;letter-spacing:0px;word-spacing:0px;display:inline;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.465361px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" - x="47.822815" + x="44.647812" y="-124.55183" id="text17738" transform="rotate(-90)" inkscape:export-filename="C:\src\ghdl\docs\block_diagrams\ad9208_dual_ebz\ad9208_vcu118_clocking.png">HMC_7044 + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:8.14381px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke:none;stroke-width:0.465361px;stroke-opacity:1">HMC7044 ` - - :adi:`UG-1829, Evaluation Board User Guide ` + - :adi:`UG-1578, AD9084/AD9088 Device User Guide ` + - :adi:`UG-2326, Evaluating the AD9084 Apollo MxFE Quad, 16-Bit 28GSPS RF DAC and Quad 12-Bit, 20GSPS RF ADC ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -916,7 +925,7 @@ HDL related - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` - :ref:`ad_ip_jesd204_tpl_dac` -- :dokuwiki:`[Wiki] Generic JESD204B block designs ` +- :ref:`generic_jesd_bds` - :ref:`jesd204` Software related