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projects: ad9084_ebz: common: ad9084_ebz_bd.tcl: Migrate to inline utility cores
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
1 parent b1098c4 commit d46119d

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projects/ad9084_ebz/common/ad9084_ebz_bd.tcl

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -263,7 +263,7 @@ if {$HSCI_ENABLE} {
263263
ad_connect hsci_phy/t_data_out GND
264264
ad_connect hsci_phy/t_clk_out GND
265265

266-
ad_ip_instance xlconcat hsci_pll_locked_concat [list \
266+
ad_ip_instance ilconcat hsci_pll_locked_concat [list \
267267
NUM_PORTS ${HSCI_BANKS} \
268268
]
269269
ad_connect hsci_pll_locked_concat/In0 hsci_phy/bank0_pll_locked
@@ -391,10 +391,10 @@ if {$ADI_PHY_SEL} {
391391
ad_connect tx_resetdone jesd204_phy/tx_resetdone
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393393
# gt powergood
394-
ad_ip_instance xlconcat gt_powergood_concat [list \
394+
ad_ip_instance ilconcat gt_powergood_concat [list \
395395
NUM_PORTS 2 \
396396
]
397-
ad_ip_instance util_reduced_logic gt_powergood_and [list \
397+
ad_ip_instance ilreduced_logic gt_powergood_and [list \
398398
C_SIZE $num_quads \
399399
]
400400
ad_connect jesd204_phy/gtpowergood gt_powergood_concat/In0
@@ -1076,7 +1076,7 @@ ad_connect ext_sync_in rx_apollo_tpl_core/adc_tpl_core/adc_sync_in
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ad_ip_parameter tx_apollo_tpl_core/dac_tpl_core CONFIG.EXT_SYNC 1
10771077
ad_connect ext_sync_in tx_apollo_tpl_core/dac_tpl_core/dac_sync_in
10781078

1079-
ad_ip_instance util_vector_logic manual_sync_or [list \
1079+
ad_ip_instance ilvector_logic manual_sync_or [list \
10801080
C_SIZE 1 \
10811081
C_OPERATION {or} \
10821082
]
@@ -1096,15 +1096,15 @@ if {$ASYMMETRIC_A_B_MODE == 0} {
10961096
ad_ip_parameter tx_b_apollo_tpl_core/dac_tpl_core CONFIG.EXT_SYNC 1
10971097
ad_connect ext_sync_in tx_b_apollo_tpl_core/dac_tpl_core/dac_sync_in
10981098

1099-
ad_ip_instance util_vector_logic manual_sync_or_b [list \
1099+
ad_ip_instance ilvector_logic manual_sync_or_b [list \
11001100
C_SIZE 1 \
11011101
C_OPERATION {or} \
11021102
]
11031103

11041104
ad_connect rx_b_apollo_tpl_core/adc_tpl_core/adc_sync_manual_req_out manual_sync_or_b/Op1
11051105
ad_connect tx_b_apollo_tpl_core/dac_tpl_core/dac_sync_manual_req_out manual_sync_or_b/Op2
11061106

1107-
ad_ip_instance util_vector_logic manual_sync_or_res [list \
1107+
ad_ip_instance ilvector_logic manual_sync_or_res [list \
11081108
C_SIZE 1 \
11091109
C_OPERATION {or} \
11101110
]
@@ -1119,17 +1119,17 @@ if {$ASYMMETRIC_A_B_MODE == 0} {
11191119
}
11201120

11211121
# Reset pack cores
1122-
ad_ip_instance util_reduced_logic cpack_rst_logic
1122+
ad_ip_instance ilreduced_logic cpack_rst_logic
11231123
ad_ip_parameter cpack_rst_logic config.c_operation {or}
11241124
ad_ip_parameter cpack_rst_logic config.c_size {3}
11251125

1126-
ad_ip_instance util_vector_logic rx_do_rstout_logic
1126+
ad_ip_instance ilvector_logic rx_do_rstout_logic
11271127
ad_ip_parameter rx_do_rstout_logic config.c_operation {not}
11281128
ad_ip_parameter rx_do_rstout_logic config.c_size {1}
11291129

11301130
ad_connect $adc_data_offload_name/s_axis_tready rx_do_rstout_logic/Op1
11311131

1132-
ad_ip_instance xlconcat cpack_reset_sources
1132+
ad_ip_instance ilconcat cpack_reset_sources
11331133
ad_ip_parameter cpack_reset_sources config.num_ports {3}
11341134
ad_connect rx_device_clk_rstgen/peripheral_reset cpack_reset_sources/in0
11351135
ad_connect rx_apollo_tpl_core/adc_tpl_core/adc_rst cpack_reset_sources/in1
@@ -1139,17 +1139,17 @@ ad_connect cpack_reset_sources/dout cpack_rst_logic/op1
11391139
ad_connect cpack_rst_logic/res util_apollo_cpack/reset
11401140

11411141
if {$ASYMMETRIC_A_B_MODE} {
1142-
ad_ip_instance util_reduced_logic cpack_b_rst_logic
1142+
ad_ip_instance ilreduced_logic cpack_b_rst_logic
11431143
ad_ip_parameter cpack_b_rst_logic config.c_operation {or}
11441144
ad_ip_parameter cpack_b_rst_logic config.c_size {3}
11451145

1146-
ad_ip_instance util_vector_logic rx_b_do_rstout_logic
1146+
ad_ip_instance ilvector_logic rx_b_do_rstout_logic
11471147
ad_ip_parameter rx_b_do_rstout_logic config.c_operation {not}
11481148
ad_ip_parameter rx_b_do_rstout_logic config.c_size {1}
11491149

11501150
ad_connect $adc_b_data_offload_name/s_axis_tready rx_b_do_rstout_logic/Op1
11511151

1152-
ad_ip_instance xlconcat cpack_b_reset_sources
1152+
ad_ip_instance ilconcat cpack_b_reset_sources
11531153
ad_ip_parameter cpack_b_reset_sources config.num_ports {3}
11541154
ad_connect rx_b_device_clk_rstgen/peripheral_reset cpack_b_reset_sources/in0
11551155
ad_connect rx_b_apollo_tpl_core/adc_tpl_core/adc_rst cpack_b_reset_sources/in1
@@ -1160,11 +1160,11 @@ if {$ASYMMETRIC_A_B_MODE} {
11601160
}
11611161

11621162
# Reset unpack cores
1163-
ad_ip_instance util_reduced_logic upack_rst_logic
1163+
ad_ip_instance ilreduced_logic upack_rst_logic
11641164
ad_ip_parameter upack_rst_logic config.c_operation {or}
11651165
ad_ip_parameter upack_rst_logic config.c_size {2}
11661166

1167-
ad_ip_instance xlconcat upack_reset_sources
1167+
ad_ip_instance ilconcat upack_reset_sources
11681168
ad_ip_parameter upack_reset_sources config.num_ports {2}
11691169
ad_connect tx_device_clk_rstgen/peripheral_reset upack_reset_sources/in0
11701170
ad_connect tx_apollo_tpl_core/dac_tpl_core/dac_rst upack_reset_sources/in1
@@ -1173,11 +1173,11 @@ ad_connect upack_reset_sources/dout upack_rst_logic/op1
11731173
ad_connect upack_rst_logic/res util_apollo_upack/reset
11741174

11751175
if {$ASYMMETRIC_A_B_MODE} {
1176-
ad_ip_instance util_reduced_logic upack_b_rst_logic
1176+
ad_ip_instance ilreduced_logic upack_b_rst_logic
11771177
ad_ip_parameter upack_b_rst_logic config.c_operation {or}
11781178
ad_ip_parameter upack_b_rst_logic config.c_size {2}
11791179

1180-
ad_ip_instance xlconcat upack_b_reset_sources
1180+
ad_ip_instance ilconcat upack_b_reset_sources
11811181
ad_ip_parameter upack_b_reset_sources config.num_ports {2}
11821182
ad_connect tx_b_device_clk_rstgen/peripheral_reset upack_b_reset_sources/in0
11831183
ad_connect tx_b_apollo_tpl_core/dac_tpl_core/dac_rst upack_b_reset_sources/in1

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