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library: jesd204: fec: Update licenses and cleanup
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
1 parent 316c9c3 commit c7c55d6

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+165
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lines changed

‎library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc‎

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,6 @@ set_property ASYNC_REG TRUE \
2020

2121
set_false_path \
2222
-to [get_cells i_up_rx/gen_lane[*].i_up_rx_lane/up_status_latency_reg[*]]
23-
# -to [get_cells -hierarchical * -filter {NAME=~datapath/datapath_rx/jesd204_rx_link_layer/link_gen[*].jesd204c_rx/axi_jesd204_rx/i_up_rx/gen_lane[*].i_up_rx_lane/up_status_latency_reg[*] && IS_SEQUENTIAL}]
24-
2523

2624
set_false_path \
2725
-from [get_pins {i_up_rx/i_cdc_status/in_toggle_d1_reg/C}] \
@@ -63,12 +61,6 @@ set_false_path \
6361
-from [get_pins {i_sync_frame_align_err/cdc_hold_reg*/C}] \
6462
-to [get_pins {i_sync_frame_align_err/out_event_reg*/D}]
6563

66-
# Don't place them too far appart
67-
# set_max_delay -datapath_only \
68-
# -from [get_pins {i_up_rx/i_cdc_status/cdc_hold_reg[*]/C}] \
69-
# -to [get_pins {i_up_rx/i_cdc_status/out_data_reg[*]/D}] \
70-
# [get_property -min PERIOD $axi_clk]
71-
7264
set_false_path \
7365
-from [get_pins {i_up_rx/i_cdc_status/cdc_hold_reg[*]/C}] \
7466
-to [get_pins {i_up_rx/i_cdc_status/out_data_reg[*]/D}]
@@ -77,11 +69,6 @@ set_false_path \
7769
-from $core_clk \
7870
-to [get_pins {i_up_rx/*i_up_rx_lane/i_cdc_status_ready/cdc_sync_stage1_reg*/D}]
7971

80-
# set_max_delay -datapath_only \
81-
# -from [get_pins {i_up_rx/i_cdc_cfg/cdc_hold_reg[*]/C}] \
82-
# -to [get_pins {i_up_rx/i_cdc_cfg/out_data_reg[*]/D}] \
83-
# [get_property -min PERIOD $core_clk]
84-
8572
set_false_path \
8673
-from [get_pins {i_up_rx/i_cdc_cfg/cdc_hold_reg[*]/C}] \
8774
-to [get_pins {i_up_rx/i_cdc_cfg/out_data_reg[*]/D}]
@@ -119,24 +106,19 @@ set_false_path \
119106
set_false_path \
120107
-from [get_pins {i_up_common/up_cfg_*_reg*/C}] \
121108
-to [get_pins {i_up_common/core_cfg_*_reg*/D}]
122-
# [get_property -min PERIOD $core_clk]
123109

124110
set_false_path \
125111
-from [get_pins {i_up_common/up_cfg_*_reg*/C}] \
126112
-to [get_pins {i_up_common/device_cfg_*_reg*/D}]
127-
# [get_property -min PERIOD $device_clk]
128113

129114
set_false_path \
130115
-from [get_pins {i_up_rx/up_cfg_*_reg*/C}] \
131116
-to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}]
132-
# [get_property -min PERIOD $core_clk]
133117

134118
set_false_path \
135119
-from [get_pins {i_up_rx/up_cfg_*_reg*/C}] \
136120
-to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}]
137-
# [get_property -min PERIOD $device_clk]
138121

139122
set_false_path \
140123
-from [get_pins {i_up_sysref/up_cfg_*_reg*/C}] \
141124
-to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}]
142-
# [get_property -min PERIOD $device_clk]

‎library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc‎

Lines changed: 7 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2017, 2018, 2021 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2017, 2018, 2021, 2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIJESD204
44
###############################################################################
55

@@ -63,64 +63,29 @@ set_false_path \
6363
set_false_path \
6464
-to [get_pins {i_up_common/up_core_reset_ext_synchronizer_vector_reg[*]/PRE}]
6565

66-
# set_max_delay -datapath_only \
67-
# -from [get_pins {i_up_common/up_cfg_*_reg*/C}] \
68-
# -to [get_pins {i_up_common/core_cfg_*_reg*/D}] \
69-
# [get_property -min PERIOD $core_clk]
70-
71-
# set_max_delay -datapath_only \
72-
# -from [get_pins {i_up_common/up_cfg_*_reg*/C}] \
73-
# -to [get_pins {i_up_common/device_cfg_*_reg*/D}] \
74-
# [get_property -min PERIOD $device_clk]
75-
76-
# set_max_delay -datapath_only \
77-
# -from [get_pins {i_up_tx/up_cfg_ilas_data_*_reg*/C}] \
78-
# -to [get_cells {i_up_tx/*core_ilas_config_data_reg*}] \
79-
# [get_property -min PERIOD $core_clk]
80-
81-
# set_max_delay -datapath_only \
82-
# -from [get_pins {i_up_tx/up_cfg_*_reg*/C}] \
83-
# -to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \
84-
# [get_property -min PERIOD $core_clk]
85-
86-
# set_max_delay -datapath_only \
87-
# -from [get_pins {i_up_tx/up_cfg_*_reg*/C}] \
88-
# -to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}] \
89-
# [get_property -min PERIOD $device_clk]
90-
91-
# set_max_delay -datapath_only \
92-
# -from [get_pins {i_up_sysref/up_cfg_*_reg*/C}] \
93-
# -to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}] \
94-
# [get_property -min PERIOD $device_clk]
95-
96-
97-
98-
9966
set_false_path \
10067
-from [get_pins {i_up_common/up_cfg_*_reg*/C}] \
101-
-to [get_pins {i_up_common/core_cfg_*_reg*/D}]
68+
-to [get_pins {i_up_common/core_cfg_*_reg*/D}]
10269

10370
set_false_path \
10471
-from [get_pins {i_up_common/up_cfg_*_reg*/C}] \
105-
-to [get_pins {i_up_common/device_cfg_*_reg*/D}]
72+
-to [get_pins {i_up_common/device_cfg_*_reg*/D}]
10673

10774
set_false_path \
10875
-from [get_pins {i_up_tx/up_cfg_ilas_data_*_reg*/C}] \
109-
-to [get_cells {i_up_tx/*core_ilas_config_data_reg*}]
76+
-to [get_cells {i_up_tx/*core_ilas_config_data_reg*}]
11077

11178
set_false_path \
11279
-from [get_pins {i_up_tx/up_cfg_*_reg*/C}] \
113-
-to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}]
80+
-to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}]
11481

11582
set_false_path \
11683
-from [get_pins {i_up_tx/up_cfg_*_reg*/C}] \
117-
-to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}]
84+
-to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}]
11885

11986
set_false_path \
12087
-from [get_pins {i_up_sysref/up_cfg_*_reg*/C}] \
121-
-to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}]
122-
123-
88+
-to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}]
12489

12590
set_false_path \
12691
-from [get_pins {i_up_tx/i_cdc_manual_sync_request/out_toggle_d1_reg/C}] \

‎library/jesd204/jesd204_common/lfsr_input.sv‎

Lines changed: 6 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -1,46 +1,9 @@
1-
//
2-
// The ADI JESD204 Core is released under the following license, which is
3-
// different than all other HDL cores in this repository.
4-
//
5-
// Please read this, and understand the freedoms and responsibilities you have
6-
// by using this source code/core.
7-
//
8-
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
9-
//
10-
// This core is free software, you can use run, copy, study, change, ask
11-
// questions about and improve this core. Distribution of source, or resulting
12-
// binaries (including those inside an FPGA or ASIC) require you to release the
13-
// source of the entire project (excluding the system libraries provide by the
14-
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
15-
// License version 2 as published by the Free Software Foundation.
16-
//
17-
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
18-
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
19-
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20-
//
21-
// You should have received a copy of the GNU General Public License version 2
22-
// along with this source code, and binary. If not, see
23-
// <http://www.gnu.org/licenses/>.
24-
//
25-
// Commercial licenses (with commercial support) of this JESD204 core are also
26-
// available under terms different than the General Public License. (e.g. they
27-
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
28-
// core with any corresponding source code.) For these alternate terms you must
29-
// purchase a license from Analog Devices Technology Licensing Office. Users
30-
// interested in such a license should contact jesd204-licensing@analog.com for
31-
// more information. This commercial license is sub-licensable (if you purchase
32-
// chips from Analog Devices, incorporate them into your PCB level product, and
33-
// purchase a JESD204 license, end users of your product will also have a
34-
// license to use this core in a commercial setting without releasing their
35-
// source code).
36-
//
37-
// In addition, we kindly ask you to acknowledge ADI in any program, application
38-
// or publication in which you use this JESD204 HDL core. (You are not required
39-
// to do so; it is up to your common sense to decide whether you want to comply
40-
// with this request or not.) For general publications, we suggest referencing :
41-
// “The design and implementation of the JESD204 HDL Core used in this project
42-
// is copyright © 2016-2017, Analog Devices, Inc.”
43-
//
1+
// ***************************************************************************
2+
// ***************************************************************************
3+
// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
4+
// SPDX short identifier: ADIJESD204
5+
// ***************************************************************************
6+
// ***************************************************************************
447

458

469
`timescale 1ns / 100ps

‎library/jesd204/jesd204_rx/jesd204_fec_decode.sv‎

Lines changed: 11 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1,47 +1,9 @@
1-
//
2-
// The ADI JESD204 Core is released under the following license, which is
3-
// different than all other HDL cores in this repository.
4-
//
5-
// Please read this, and understand the freedoms and responsibilities you have
6-
// by using this source code/core.
7-
//
8-
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
9-
//
10-
// This core is free software, you can use run, copy, study, change, ask
11-
// questions about and improve this core. Distribution of source, or resulting
12-
// binaries (including those inside an FPGA or ASIC) require you to release the
13-
// source of the entire project (excluding the system libraries provide by the
14-
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
15-
// License version 2 as published by the Free Software Foundation.
16-
//
17-
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
18-
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
19-
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20-
//
21-
// You should have received a copy of the GNU General Public License version 2
22-
// along with this source code, and binary. If not, see
23-
// <http://www.gnu.org/licenses/>.
24-
//
25-
// Commercial licenses (with commercial support) of this JESD204 core are also
26-
// available under terms different than the General Public License. (e.g. they
27-
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
28-
// core with any corresponding source code.) For these alternate terms you must
29-
// purchase a license from Analog Devices Technology Licensing Office. Users
30-
// interested in such a license should contact jesd204-licensing@analog.com for
31-
// more information. This commercial license is sub-licensable (if you purchase
32-
// chips from Analog Devices, incorporate them into your PCB level product, and
33-
// purchase a JESD204 license, end users of your product will also have a
34-
// license to use this core in a commercial setting without releasing their
35-
// source code).
36-
//
37-
// In addition, we kindly ask you to acknowledge ADI in any program, application
38-
// or publication in which you use this JESD204 HDL core. (You are not required
39-
// to do so; it is up to your common sense to decide whether you want to comply
40-
// with this request or not.) For general publications, we suggest referencing :
41-
// “The design and implementation of the JESD204 HDL Core used in this project
42-
// is copyright © 2016-2017, Analog Devices, Inc.”
43-
//
44-
1+
// ***************************************************************************
2+
// ***************************************************************************
3+
// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
4+
// SPDX short identifier: ADIJESD204
5+
// ***************************************************************************
6+
// ***************************************************************************
457

468
`timescale 1ns / 100ps
479

@@ -92,7 +54,7 @@ module jesd204_fec_decode #(
9254
logic [BUFFER_ADDR_WIDTH-1:0] buf_rd_addr;
9355
logic [DATA_WIDTH-1:0] buf_wr_data;
9456
logic [DATA_WIDTH-1:0] buf_rd_data;
95-
logic [DATA_WIDTH-1:0] buf_rd_data_d;
57+
// logic [DATA_WIDTH-1:0] buf_rd_data_d;
9658
logic [3:1] eomb_d;
9759
logic data_in_en;
9860
logic fec_in_en;
@@ -135,7 +97,8 @@ module jesd204_fec_decode #(
13597
// Data buffer
13698
ad_mem_dist #(
13799
.RAM_WIDTH (DATA_WIDTH),
138-
.RAM_ADDR_BITS (BUFFER_ADDR_WIDTH)
100+
.RAM_ADDR_BITS (BUFFER_ADDR_WIDTH),
101+
.REGISTERED_OUTPUT (1)
139102
) data_buffer (
140103
.rd_data (buf_rd_data),
141104
.clk (clk),
@@ -259,7 +222,7 @@ module jesd204_fec_decode #(
259222

260223
always_ff @(posedge clk) begin
261224
error_syndrome_next_d <= error_syndrome_next;
262-
buf_rd_data_d <= buf_rd_data;
225+
// buf_rd_data_d <= buf_rd_data;
263226
end
264227

265228
// Error is trapped if the MSb of the syndrome is 1 and bits 16:0 of the syndrome are 0
@@ -301,7 +264,7 @@ module jesd204_fec_decode #(
301264
// Correct data by XORing with FEC syndrome
302265
// Output corrected data
303266
always_ff @(posedge clk) begin
304-
data_out <= buf_rd_data_d ^ error_bits[DATA_WIDTH-1:0] ^ error_bits_prev;
267+
data_out <= buf_rd_data ^ error_bits[DATA_WIDTH-1:0] ^ error_bits_prev;
305268
data_out_valid <= data_out_en_d[1];
306269
end
307270

‎library/jesd204/jesd204_rx/jesd204_rx.xdc‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,7 @@
1+
###############################################################################
2+
## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
3+
# SPDX short identifier: ADIBSD
4+
###############################################################################
5+
16
set_false_path -through [get_ports {cfg_*}]
2-
set_false_path -through [get_ports {core_cfg_*}]
7+
set_false_path -through [get_ports {core_cfg_*}]

‎library/jesd204/jesd204_rx/jesd204_rx_fec_lfsr.sv‎

Lines changed: 8 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -1,46 +1,9 @@
1-
//
2-
// The ADI JESD204 Core is released under the following license, which is
3-
// different than all other HDL cores in this repository.
4-
//
5-
// Please read this, and understand the freedoms and responsibilities you have
6-
// by using this source code/core.
7-
//
8-
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
9-
//
10-
// This core is free software, you can use run, copy, study, change, ask
11-
// questions about and improve this core. Distribution of source, or resulting
12-
// binaries (including those inside an FPGA or ASIC) require you to release the
13-
// source of the entire project (excluding the system libraries provide by the
14-
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
15-
// License version 2 as published by the Free Software Foundation.
16-
//
17-
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
18-
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
19-
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20-
//
21-
// You should have received a copy of the GNU General Public License version 2
22-
// along with this source code, and binary. If not, see
23-
// <http://www.gnu.org/licenses/>.
24-
//
25-
// Commercial licenses (with commercial support) of this JESD204 core are also
26-
// available under terms different than the General Public License. (e.g. they
27-
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
28-
// core with any corresponding source code.) For these alternate terms you must
29-
// purchase a license from Analog Devices Technology Licensing Office. Users
30-
// interested in such a license should contact jesd204-licensing@analog.com for
31-
// more information. This commercial license is sub-licensable (if you purchase
32-
// chips from Analog Devices, incorporate them into your PCB level product, and
33-
// purchase a JESD204 license, end users of your product will also have a
34-
// license to use this core in a commercial setting without releasing their
35-
// source code).
36-
//
37-
// In addition, we kindly ask you to acknowledge ADI in any program, application
38-
// or publication in which you use this JESD204 HDL core. (You are not required
39-
// to do so; it is up to your common sense to decide whether you want to comply
40-
// with this request or not.) For general publications, we suggest referencing :
41-
// “The design and implementation of the JESD204 HDL Core used in this project
42-
// is copyright © 2016-2017, Analog Devices, Inc.”
43-
//
1+
// ***************************************************************************
2+
// ***************************************************************************
3+
// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
4+
// SPDX short identifier: ADIJESD204
5+
// ***************************************************************************
6+
// ***************************************************************************
447

458

469
`timescale 1ns / 100ps
@@ -117,10 +80,10 @@ module jesd204_rx_fec_lfsr #(
11780

11881
// Shift register input is output of previous shift register value,
11982
// or load value if load enabled
120-
always @(posedge clk) begin
83+
always @(posedge clk) begin
12184
if(rst) begin
12285
shift_reg_in_start <= RESET_VAL;
123-
end else begin
86+
end else begin
12487
if(load_en) begin
12588
shift_reg_in_start <= load_data;
12689
end else if(shift_en) begin

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