projects: ad9084_ebz: Change spi to 3 wire

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>

Author: bluncan

projects/ad9084_ebz/common/ad9084_ebz_spi.v

@@ -6,7 +6,6 @@
 
 PROJECT_NAME := ad9084_ebz_fm87
 
-M_DEPS += ../common/ad9084_ebz_spi.v
 M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/intel/adcfifo_qsys.tcl
 M_DEPS += ../../common/fm87/system_qsys.tcl

projects/ad9084_ebz/fm87/Makefile

@@ -70,7 +70,6 @@ source $ad_hdl_dir/projects/common/fm87/fm87_plddr_system_assign.tcl
 set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_3w_spi.v
 set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v
 set_global_assignment -name VERILOG_FILE $ad_hdl_dir/projects/common/fm87/gpio_slave.v
-set_global_assignment -name VERILOG_FILE ../common/ad9084_ebz_spi.v
 
 set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)"    -to fpga_refclk_in
 set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to syncinb_a0

projects/ad9084_ebz/fm87/system_project.tcl

@@ -223,15 +223,13 @@ module system_top #(
   assign spi2_cs[5:0] = spi_csn[5:0];
   assign spi2_sclk    = spi_clk;
 
-  ad9084_ebz_spi #(
-    .NUM_OF_SLAVES(2),
-    .IS_4WIRE(2'b01)
+  ad_3w_spi #(
+    .NUM_OF_SLAVES(2)
   ) i_spi (
     .spi_csn (spi_csn[1:0]),
     .spi_clk (spi_clk),
     .spi_mosi (spi_sdio),
     .spi_miso (spi_sdo),
-    .spi_miso_in (spi2_sdo),
     .spi_sdio (spi2_sdio));
 
   assign dut_csb  = apollo_spi_csn[0];

projects/ad9084_ebz/fm87/system_top.v

@@ -8,7 +8,6 @@ PROJECT_NAME := ad9084_ebz_vck190
 
 M_DEPS += ../common/versal_transceiver.tcl
 M_DEPS += ../common/versal_hsci_phy.tcl
-M_DEPS += ../common/ad9084_ebz_spi.v
 M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
 M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
@@ -19,6 +18,7 @@ M_DEPS += ../../ad9084_ebz/common/ad9084_ebz_bd.tcl
 M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
 M_DEPS += ../../../library/util_cdc/sync_bits.v
 M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_3w_spi.v
 M_DEPS += ../../../projects/common/xilinx/data_offload_bd.tcl
 M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
 

projects/ad9084_ebz/vck190/Makefile

@@ -78,8 +78,8 @@ adi_project_files ad9084_ebz_vck190 [list \
   "system_constr.xdc" \
   "timing_constr.tcl" \
   "../common/versal_hsci_phy.tcl" \
-  "../common/ad9084_ebz_spi.v" \
   "../common/versal_transceiver.tcl" \
+  "$ad_hdl_dir/library/common/ad_3w_spi.v" \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vck190/vck190_system_constr.xdc" ]
 

projects/ad9084_ebz/vck190/system_project.tcl

@@ -266,15 +266,13 @@ module system_top #(
   assign spi2_cs[4] = spi_csn[2];
   assign spi2_sclk    = spi_clk;
 
-  ad9084_ebz_spi #(
-    .NUM_OF_SLAVES(3),
-    .IS_4WIRE(3'b101)
+  ad_3w_spi #(
+    .NUM_OF_SLAVES(3)
   ) i_spi (
     .spi_csn (spi_csn[2:0]),
     .spi_clk (spi_clk),
     .spi_mosi (spi_sdio),
     .spi_miso (spi_sdo),
-    .spi_miso_in (spi2_sdo),
     .spi_sdio (spi2_sdio));
 
   assign dut_csb  = apollo_spi_csn[0];

projects/ad9084_ebz/vck190/system_top.v

@@ -8,7 +8,6 @@ PROJECT_NAME := ad9084_ebz_vcu118
 
 M_DEPS += timing_constr.xdc
 M_DEPS += ../common/versal_hsci_phy.tcl
-M_DEPS += ../common/ad9084_ebz_spi.v
 M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
 M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
@@ -19,6 +18,7 @@ M_DEPS += ../../../library/xilinx/common/ad_rst_constr.xdc
 M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
 M_DEPS += ../../../library/common/ad_rst.v
 M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_3w_spi.v
 M_DEPS += ../../../projects/common/xilinx/data_offload_bd.tcl
 M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
 

projects/ad9084_ebz/vcu118/Makefile

@@ -76,9 +76,9 @@ adi_project_files ad9084_ebz_vcu118 [list \
   "system_constr.xdc"\
   "timing_constr.xdc"\
   "../common/hsci_phy_top.sv"\
-  "../common/ad9084_ebz_spi.v"\
   "$ad_hdl_dir/library/common/ad_rst.v"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/library/common/ad_3w_spi.v" \
   "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc"\
   "$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ]
 create_ip -name high_speed_selectio_wiz -vendor xilinx.com -library ip -version 3.6 -module_name high_speed_selectio_wiz_0

projects/ad9084_ebz/vcu118/system_project.tcl

@@ -312,15 +312,13 @@ module system_top #(
   assign spi2_cs[5:0] = spi_csn[5:0];
   assign spi2_sclk    = spi_clk;
 
-  ad9084_ebz_spi #(
-    .NUM_OF_SLAVES(2),
-    .IS_4WIRE(2'b01)
+  ad_3w_spi #(
+    .NUM_OF_SLAVES(3)
   ) i_spi (
-    .spi_csn (spi_csn[1:0]),
+    .spi_csn (spi_csn[2:0]),
     .spi_clk (spi_clk),
     .spi_mosi (spi_sdio),
     .spi_miso (spi_sdo),
-    .spi_miso_in (spi2_sdo),
     .spi_sdio (spi2_sdio));
 
   assign dut_csb  = apollo_spi_csn[0];