44# ##############################################################################
55
66source $ad_hdl_dir /library/jesd204/scripts/jesd204.tcl
7+ source $ad_hdl_dir /projects/common/xilinx/data_offload_bd.tcl
78
89set JESD_M $ad_project_params(JESD_M)
910set JESD_L $ad_project_params(JESD_L)
@@ -16,11 +17,9 @@ set SAMPLE_WIDTH $ad_project_params(JESD_NP)
1617
1718set DAC_DATA_WIDTH [expr $NUM_OF_LANES * 32]
1819set SAMPLES_PER_CHANNEL [expr $DAC_DATA_WIDTH / $NUM_OF_CONVERTERS / $SAMPLE_WIDTH ]
19-
2020set MAX_NUM_OF_LANES 8
21- # Top level ports
2221
23- create_bd_port -dir I dac_fifo_bypass
22+ set dac_offload_name dac_data_offload
2423
2524# dac peripherals
2625
@@ -55,10 +54,15 @@ ad_ip_instance axi_dmac dac_dma [list \
5554 CACHE_COHERENT $CACHE_COHERENCY \
5655]
5756
58- ad_dacfifo_create axi_dac_fifo \
59- $DAC_DATA_WIDTH \
60- $dac_dma_data_width \
61- $dac_fifo_address_width
57+ ad_data_offload_create $dac_offload_name \
58+ 1 \
59+ $dac_offload_type \
60+ $dac_offload_size \
61+ $dac_dma_data_width \
62+ $DAC_DATA_WIDTH
63+
64+ ad_ip_parameter $dac_offload_name /i_data_offload CONFIG.SYNC_EXT_ADD_INTERNAL_CDC 0
65+ ad_connect $dac_offload_name /sync_ext GND
6266
6367# shared transceiver core
6468
@@ -106,28 +110,24 @@ for {set i 0} {$i < $NUM_OF_CONVERTERS} {incr i} {
106110 ad_connect dac_jesd204_transport/dac_enable_$i dac_upack/enable_$i
107111}
108112
109- ad_connect util_dac_jesd204_xcvr/tx_out_clk_0 axi_dac_fifo/dac_clk
110- ad_connect dac_jesd204_link_rstgen/peripheral_reset axi_dac_fifo/dac_rst
111- ad_connect dac_upack/s_axis_valid VCC
112- ad_connect dac_upack/s_axis_ready axi_dac_fifo/dac_valid
113- ad_connect dac_upack/s_axis_data axi_dac_fifo/dac_data
114- ad_connect dac_jesd204_transport/dac_dunf axi_dac_fifo/dac_dunf
115- ad_connect sys_cpu_clk axi_dac_fifo/dma_clk
116- ad_connect sys_cpu_reset axi_dac_fifo/dma_rst
113+ ad_connect util_dac_jesd204_xcvr/tx_out_clk_0 $dac_offload_name /m_axis_aclk
114+ ad_connect dac_jesd204_link_rstgen/peripheral_aresetn $dac_offload_name /m_axis_aresetn
115+ ad_connect dac_upack/s_axis $dac_offload_name /m_axis
116+ ad_connect dac_jesd204_transport/dac_dunf dac_upack/fifo_rd_underflow
117+ ad_connect sys_cpu_clk $dac_offload_name /s_axis_aclk
118+ ad_connect sys_cpu_resetn $dac_offload_name /s_axis_aresetn
117119ad_connect sys_cpu_clk dac_dma/m_axis_aclk
118120ad_connect sys_cpu_resetn dac_dma/m_src_axi_aresetn
119- ad_connect axi_dac_fifo/dma_xfer_req dac_dma/m_axis_xfer_req
120- ad_connect axi_dac_fifo/dma_ready dac_dma/m_axis_ready
121- ad_connect axi_dac_fifo/dma_data dac_dma/m_axis_data
122- ad_connect axi_dac_fifo/dma_valid dac_dma/m_axis_valid
123- ad_connect axi_dac_fifo/dma_xfer_last dac_dma/m_axis_last
121+ ad_connect $dac_offload_name /init_req dac_dma/m_axis_xfer_req
122+ ad_connect $dac_offload_name /s_axis dac_dma/m_axis
124123
125124# interconnect (cpu)
126125
127126ad_cpu_interconnect 0x44A60000 dac_jesd204_xcvr
128127ad_cpu_interconnect 0x44A04000 dac_jesd204_transport
129128ad_cpu_interconnect 0x44A90000 dac_jesd204_link
130129ad_cpu_interconnect 0x7c420000 dac_dma
130+ ad_cpu_interconnect 0x7c430000 $dac_offload_name
131131
132132# interconnect (mem/dac)
133133
@@ -143,6 +143,3 @@ if {$CACHE_COHERENCY} {
143143
144144ad_cpu_interrupt ps-10 mb-15 dac_jesd204_link/irq
145145ad_cpu_interrupt ps-12 mb-13 dac_dma/irq
146-
147- ad_connect axi_dac_fifo/bypass dac_fifo_bypass
148-
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