Skip to content

Commit 2a1d9bb

Browse files
bluncanbluncan
committed
projects: ad9084_fmca_ebz: Initial commit
Adds AD9084-EBZ (Apollo) base design for the following carriers: - vcu118 - vck190 - vpk180 - fm87 Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
1 parent 8a7241f commit 2a1d9bb

31 files changed

+7318
-0
lines changed

‎projects/ad9084_ebz/Makefile‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
####################################################################################
2+
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
3+
### SPDX short identifier: BSD-1-Clause
4+
## Auto-generated, do not modify!
5+
####################################################################################
6+
7+
include ../scripts/project-toplevel.mk

‎projects/ad9084_ebz/common/ad9084_ebz_bd.tcl‎

Lines changed: 1219 additions & 0 deletions
Large diffs are not rendered by default.

‎projects/ad9084_ebz/common/ad9084_ebz_qsys.tcl‎

Lines changed: 646 additions & 0 deletions
Large diffs are not rendered by default.

‎projects/ad9084_ebz/common/ad9084_ebz_spi.v‎

Lines changed: 92 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,92 @@
1+
// ***************************************************************************
2+
// ***************************************************************************
3+
// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
4+
//
5+
// In this HDL repository, there are many different and unique modules, consisting
6+
// of various HDL (Verilog or VHDL) components. The individual modules are
7+
// developed independently, and may be accompanied by separate and unique license
8+
// terms.
9+
//
10+
// The user should read each of these license terms, and understand the
11+
// freedoms and responsibilities that he or she has by using this source/core.
12+
//
13+
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
14+
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
15+
// A PARTICULAR PURPOSE.
16+
//
17+
// Redistribution and use of source or resulting binaries, with or without modification
18+
// of this file, are permitted under one of the following two license terms:
19+
//
20+
// 1. The GNU General Public License version 2 as published by the
21+
// Free Software Foundation, which can be found in the top level directory
22+
// of this repository (LICENSE_GPL2), and also online at:
23+
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
24+
//
25+
// OR
26+
//
27+
// 2. An ADI specific BSD license, which can be found in the top level directory
28+
// of this repository (LICENSE_ADIBSD), and also on-line at:
29+
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
30+
// This will allow to generate bit files and not release the source code,
31+
// as long as it attaches to an ADI device.
32+
//
33+
// ***************************************************************************
34+
// ***************************************************************************
35+
36+
`timescale 1ns/100ps
37+
38+
module ad9084_ebz_spi #(
39+
parameter NUM_OF_SLAVES = 8
40+
) (
41+
input [NUM_OF_SLAVES-1:0] spi_csn,
42+
input spi_clk,
43+
input spi_mosi,
44+
output spi_miso,
45+
input spi_miso_in,
46+
inout spi_sdio
47+
);
48+
49+
// internal registers
50+
51+
reg [ 5:0] spi_count = 'd0;
52+
reg spi_rd_wr_n = 'd0;
53+
reg spi_enable = 'd0;
54+
55+
// internal signals
56+
57+
wire spi_csn_s;
58+
wire spi_enable_s;
59+
60+
// check on rising edge and change on falling edge
61+
62+
assign spi_csn_s = & spi_csn;
63+
assign spi_enable_s = spi_enable & ~spi_csn_s;
64+
65+
always @(posedge spi_clk or posedge spi_csn_s) begin
66+
if (spi_csn_s == 1'b1) begin
67+
spi_count <= 6'd0;
68+
spi_rd_wr_n <= 1'd0;
69+
end else begin
70+
spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
71+
if (spi_count == 6'd0) begin
72+
spi_rd_wr_n <= spi_mosi;
73+
end
74+
end
75+
end
76+
77+
always @(negedge spi_clk or posedge spi_csn_s) begin
78+
if (spi_csn_s == 1'b1) begin
79+
spi_enable <= 1'b0;
80+
end else begin
81+
if (spi_count == 6'd16) begin
82+
spi_enable <= spi_rd_wr_n;
83+
end
84+
end
85+
end
86+
87+
// io buffer
88+
89+
assign spi_miso = (spi_csn[0] == 1'b0) ? spi_miso_in : spi_sdio;
90+
assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
91+
92+
endmodule

‎projects/ad9084_ebz/common/hsci_phy_top.sv‎

Lines changed: 131 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,131 @@
1+
// ***************************************************************************
2+
// ***************************************************************************
3+
// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
4+
//
5+
// In this HDL repository, there are many different and unique modules, consisting
6+
// of various HDL (Verilog or VHDL) components. The individual modules are
7+
// developed independently, and may be accompanied by separate and unique license
8+
// terms.
9+
//
10+
// The user should read each of these license terms, and understand the
11+
// freedoms and responsibilities that he or she has by using this source/core.
12+
//
13+
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
14+
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
15+
// A PARTICULAR PURPOSE.
16+
//
17+
// Redistribution and use of source or resulting binaries, with or without modification
18+
// of this file, are permitted under one of the following two license terms:
19+
//
20+
// 1. The GNU General Public License version 2 as published by the
21+
// Free Software Foundation, which can be found in the top level directory
22+
// of this repository (LICENSE_GPL2), and also online at:
23+
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
24+
//
25+
// OR
26+
//
27+
// 2. An ADI specific BSD license, which can be found in the top level directory
28+
// of this repository (LICENSE_ADIBSD), and also on-line at:
29+
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
30+
// This will allow to generate bit files and not release the source code,
31+
// as long as it attaches to an ADI device.
32+
//
33+
// ***************************************************************************
34+
// ***************************************************************************
35+
36+
`timescale 1ps/1ps
37+
38+
module hsci_phy_top (
39+
40+
input wire pll_inclk,
41+
input wire hsci_pll_reset,
42+
43+
output logic hsci_pclk,
44+
output logic hsci_mosi_d_p,
45+
output logic hsci_mosi_d_n,
46+
47+
input wire hsci_miso_d_p,
48+
input wire hsci_miso_d_n,
49+
50+
output logic hsci_pll_locked,
51+
52+
output logic hsci_mosi_clk_p,
53+
output logic hsci_mosi_clk_n,
54+
55+
input wire hsci_miso_clk_p,
56+
input wire hsci_miso_clk_n,
57+
58+
input wire [7:0] hsci_menc_clk,
59+
input wire [7:0] hsci_mosi_data,
60+
output logic [7:0] hsci_miso_data,
61+
62+
// Status Signals
63+
output logic vtc_rdy_bsc_tx,
64+
output logic dly_rdy_bsc_tx,
65+
output logic vtc_rdy_bsc_rx,
66+
output logic dly_rdy_bsc_rx,
67+
output logic rst_seq_done
68+
69+
);
70+
//TX
71+
logic [7:0] hsci_mosi_data_br;
72+
logic rst_seq_done_tx;
73+
logic dly_rdy_bsc0;
74+
logic vtc_rdy_bsc0;
75+
logic dly_rdy_bsc1;
76+
logic vtc_rdy_bsc1;
77+
78+
// RX
79+
logic [7:0] hsci_miso_data_br;
80+
logic [7:0] hsci_miso_clk_d;
81+
logic fifo_empty_rx;
82+
logic fifo_empty_rx_strobe;
83+
84+
// PLL
85+
logic shared_pll0_clkoutphy_out;
86+
logic pll0_clkout1;
87+
88+
assign hsci_mosi_data_br = {hsci_mosi_data[0],hsci_mosi_data[1],hsci_mosi_data[2],hsci_mosi_data[3],hsci_mosi_data[4],hsci_mosi_data[5],hsci_mosi_data[6],hsci_mosi_data[7]};
89+
90+
assign hsci_miso_data = rst_seq_done ? {hsci_miso_data_br[0],hsci_miso_data_br[1],hsci_miso_data_br[2],hsci_miso_data_br[3],hsci_miso_data_br[4],hsci_miso_data_br[5],hsci_miso_data_br[6],hsci_miso_data_br[7]}
91+
: 8'h0;
92+
93+
assign dly_rdy_bsc_tx = dly_rdy_bsc0 & dly_rdy_bsc1;
94+
assign vtc_rdy_bsc_tx = vtc_rdy_bsc0 & vtc_rdy_bsc1;
95+
96+
high_speed_selectio_wiz_0 hssio_wiz_tx_rx (
97+
.fifo_rd_clk_32 (hsci_pclk),
98+
.fifo_rd_clk_34 (hsci_pclk),
99+
.fifo_rd_en_32 (1'b0),
100+
.fifo_rd_en_34 (1'b1 & !fifo_empty_rx & rst_seq_done),
101+
.fifo_empty_32 (fifo_empty_rx_strobe),
102+
.fifo_empty_34 (fifo_empty_rx),
103+
.dly_rdy_bsc0 (dly_rdy_bsc0),
104+
.vtc_rdy_bsc0 (vtc_rdy_bsc0),
105+
.en_vtc_bsc0 (1'b1),
106+
.dly_rdy_bsc1 (dly_rdy_bsc1),
107+
.vtc_rdy_bsc1 (vtc_rdy_bsc1),
108+
.en_vtc_bsc1 (1'b1),
109+
.dly_rdy_bsc5 (dly_rdy_bsc_rx),
110+
.vtc_rdy_bsc5 (vtc_rdy_bsc_rx),
111+
.en_vtc_bsc5 (1'b1),
112+
.rst_seq_done (rst_seq_done),
113+
.shared_pll0_clkoutphy_out (shared_pll0_clkoutphy_out),
114+
.pll0_clkout0 (hsci_pclk),
115+
.rst (hsci_pll_reset),
116+
.clk (pll_inclk),
117+
.pll0_locked (hsci_pll_locked),
118+
.clk_out_p (hsci_mosi_clk_p),
119+
.data_from_fabric_clk_out_p (hsci_menc_clk),
120+
.clk_out_n (hsci_mosi_clk_n),
121+
.data_out_p (hsci_mosi_d_p),
122+
.data_from_fabric_data_out_p (hsci_mosi_data_br),
123+
.data_out_n (hsci_mosi_d_n),
124+
.clk_in_p (hsci_miso_clk_p),
125+
.data_to_fabric_clk_in_p (hsci_miso_clk_d),
126+
.clk_in_n (hsci_miso_clk_n),
127+
.data_in_p (hsci_miso_d_p),
128+
.data_to_fabric_data_in_p (hsci_miso_data_br),
129+
.data_in_n (hsci_miso_d_n));
130+
131+
endmodule

‎projects/ad9084_ebz/common/trigger_generator.v‎

Lines changed: 140 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,140 @@
1+
// ***************************************************************************
2+
// ***************************************************************************
3+
// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
4+
//
5+
// In this HDL repository, there are many different and unique modules, consisting
6+
// of various HDL (Verilog or VHDL) components. The individual modules are
7+
// developed independently, and may be accompanied by separate and unique license
8+
// terms.
9+
//
10+
// The user should read each of these license terms, and understand the
11+
// freedoms and responsibilities that he or she has by using this source/core.
12+
//
13+
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
14+
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
15+
// A PARTICULAR PURPOSE.
16+
//
17+
// Redistribution and use of source or resulting binaries, with or without modification
18+
// of this file, are permitted under one of the following two license terms:
19+
//
20+
// 1. The GNU General Public License version 2 as published by the
21+
// Free Software Foundation, which can be found in the top level directory
22+
// of this repository (LICENSE_GPL2), and also online at:
23+
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
24+
//
25+
// OR
26+
//
27+
// 2. An ADI specific BSD license, which can be found in the top level directory
28+
// of this repository (LICENSE_ADIBSD), and also on-line at:
29+
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
30+
// This will allow to generate bit files and not release the source code,
31+
// as long as it attaches to an ADI device.
32+
//
33+
// ***************************************************************************
34+
// ***************************************************************************
35+
36+
`timescale 1ns / 1ps
37+
38+
module trigger_generator (
39+
input wire sysref,
40+
input wire device_clk,
41+
input wire gpio,
42+
input wire rstn,
43+
output reg trigger
44+
);
45+
46+
localparam STATE_WIDTH = 3;
47+
localparam [STATE_WIDTH-1:0] CALIB_IDLE = 0;
48+
localparam [STATE_WIDTH-1:0] CALIB_START = 1;
49+
localparam [STATE_WIDTH-1:0] IDLE = 2;
50+
localparam [STATE_WIDTH-1:0] SYSREF_SYNC = 3;
51+
localparam [STATE_WIDTH-1:0] START = 4;
52+
localparam [STATE_WIDTH-1:0] TRIGGER = 5;
53+
54+
reg [STATE_WIDTH-1:0] curr_state = CALIB_IDLE;
55+
reg [STATE_WIDTH-1:0] next_state;
56+
reg [15:0] quarter_count = 'h0000;
57+
reg [15:0] full_count = 'h0000;
58+
reg [15:0] ratio_counter = 'h0000;
59+
reg calib_done = 'b0;
60+
reg sysref_edge = 'b0;
61+
reg sysref_r = 'b0;
62+
reg gpio_edge = 'b0;
63+
reg gpio_r = 'b0;
64+
65+
wire gpio_sync;
66+
67+
ad_rst i_gpio_sync (
68+
.rst_async (gpio),
69+
.clk (device_clk),
70+
.rstn (),
71+
.rst (gpio_sync));
72+
73+
always @* begin
74+
case(curr_state)
75+
CALIB_IDLE: next_state = (sysref_edge) ? CALIB_START : CALIB_IDLE;
76+
CALIB_START: next_state = (calib_done == 1'b1) ? IDLE : CALIB_START;
77+
IDLE: next_state = (gpio_edge == 1'b1) ? SYSREF_SYNC : IDLE;
78+
SYSREF_SYNC: next_state = (sysref_edge) ? START : SYSREF_SYNC;
79+
START: next_state = (quarter_count < (ratio_counter / 2) - 2) ? START : TRIGGER;
80+
TRIGGER: next_state = (full_count <= (ratio_counter * 2) + 2) ? TRIGGER : IDLE;
81+
default: next_state = CALIB_IDLE;
82+
endcase
83+
end
84+
85+
always @(posedge device_clk) begin
86+
if (rstn == 1'b0) begin
87+
curr_state <= CALIB_IDLE;
88+
calib_done <= 1'b0;
89+
ratio_counter <= 'h0000;
90+
end else begin
91+
curr_state <= next_state;
92+
if (curr_state == CALIB_START) begin
93+
if (sysref) begin
94+
ratio_counter <= ratio_counter + 'b1;
95+
end else begin
96+
calib_done <= 'b1;
97+
end
98+
end
99+
end
100+
end
101+
102+
always @(posedge device_clk) begin
103+
sysref_r <= sysref;
104+
sysref_edge <= (sysref && !sysref_r);
105+
end
106+
107+
always @(posedge device_clk) begin
108+
gpio_r <= gpio_sync;
109+
gpio_edge <= (gpio_sync && !gpio_r);
110+
end
111+
112+
always @(posedge device_clk) begin
113+
if (curr_state == START) begin
114+
if (quarter_count < (ratio_counter / 2) - 2) begin
115+
quarter_count <= quarter_count + 'b1;
116+
end else begin
117+
quarter_count <= 0;
118+
end
119+
end
120+
end
121+
122+
always @(posedge device_clk) begin
123+
if (curr_state == TRIGGER) begin
124+
if (full_count <= (ratio_counter * 2) + 2) begin
125+
full_count <= full_count + 'b1;
126+
end else begin
127+
full_count <= 0;
128+
end
129+
end
130+
end
131+
132+
always @(posedge device_clk) begin
133+
if (curr_state == TRIGGER) begin
134+
trigger <= 1'b1;
135+
end else begin
136+
trigger <= 1'b0;
137+
end
138+
end
139+
140+
endmodule

0 commit comments

Comments
 (0)