build.plat: allow removing src attributes from RTLIL output.

This is important for Glasgow, which uses RTLIL hash as cache key,
and expects it to be stable between CI jobs.

Author: whitequark

amaranth/build/plat.py

@@ -303,7 +303,7 @@ def iter_clock_constraints(self):
                 continue
             yield net_signal, port_signal, frequency
 
-    def toolchain_prepare(self, fragment, name, **kwargs):
+    def toolchain_prepare(self, fragment, name, *, emit_src=True, **kwargs):
         # Restrict the name of the design to a strict alphanumeric character set. Platforms will
         # interpolate the name of the design in many different contexts: filesystem paths, Python
         # scripts, Tcl scripts, ad-hoc constraint files, and so on. It is not practical to add
@@ -319,7 +319,7 @@ def toolchain_prepare(self, fragment, name, **kwargs):
         # and to incorporate the Amaranth version into generated code.
         autogenerated = "Automatically generated by Amaranth {}. Do not edit.".format(__version__)
 
-        rtlil_text, self._name_map = rtlil.convert_fragment(fragment, name=name)
+        rtlil_text, self._name_map = rtlil.convert_fragment(fragment, name=name, emit_src=emit_src)
 
         # Retrieve an override specified in either the environment or as a kwarg.
         # expected_type parameter is used to assert the type of kwargs, passing `None` will disable