amaranth.hdl: start all private names with an underscore.

This change completes commit 9dc0617 and makes all the tests pass.
It corresponds with the ongoing langauge reference documentation effort.

Fixes #781.

Author: whitequark

amaranth/asserts.py

@@ -1,4 +1,4 @@
-from .hdl.ast import AnyConst, AnySeq, Initial, Assert, Assume, Cover
+from .hdl._ast import AnyConst, AnySeq, Initial, Assert, Assume, Cover
 
 
 __all__ = ["AnyConst", "AnySeq", "Initial", "Assert", "Assume", "Cover"]

amaranth/back/rtlil.py

@@ -1,5 +1,5 @@
 from .._toolchain.yosys import *
-from ..hdl import ast, ir
+from ..hdl import _ast, _ir
 from ..lib import wiring
 from . import rtlil
 
@@ -49,12 +49,12 @@ def convert(elaboratable, name="top", platform=None, *, ports=None, emit_src=Tru
             isinstance(elaboratable.signature, wiring.Signature)):
         ports = []
         for path, member, value in elaboratable.signature.flatten(elaboratable):
-            if isinstance(value, ast.ValueCastable):
+            if isinstance(value, _ast.ValueCastable):
                 value = value.as_value()
-            if isinstance(value, ast.Value):
+            if isinstance(value, _ast.Value):
                 ports.append(value)
     elif ports is None:
         raise TypeError("The `convert()` function requires a `ports=` argument")
-    fragment = ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
+    fragment = _ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
     verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src, strip_internal_attrs=strip_internal_attrs)
     return verilog_text

amaranth/back/verilog.py

@@ -9,7 +9,7 @@
 from .. import __version__
 from .._toolchain import *
 from ..hdl import *
-from ..hdl.xfrm import DomainLowerer
+from ..hdl._xfrm import DomainLowerer
 from ..lib.cdc import ResetSynchronizer
 from ..back import rtlil, verilog
 from .res import *

amaranth/build/plat.py

@@ -1,7 +1,7 @@
 from collections import OrderedDict
 import warnings
 
-from ..hdl.ast import *
+from ..hdl._ast import *
 with warnings.catch_warnings():
     warnings.filterwarnings(action="ignore", category=DeprecationWarning)
     from ..hdl.rec import *

amaranth/build/res.py

@@ -1,6 +1,6 @@
 import argparse
 
-from .hdl.ir import Fragment
+from .hdl._ir import Fragment
 from .back import rtlil, cxxrtl, verilog
 from .sim import Simulator
 

amaranth/cli.py

@@ -1,24 +1,29 @@
-import warnings
-
-from .ast import Shape, unsigned, signed
-from .ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal
-from .dsl import Module
-from .cd import ClockDomain
-from .ir import Elaboratable, Fragment, Instance
-from .mem import Memory
-with warnings.catch_warnings():
-    warnings.filterwarnings(action="ignore", category=DeprecationWarning)
-    from .rec import Record
-from .xfrm import DomainRenamer, ResetInserter, EnableInserter
+from ._ast import Shape, unsigned, signed, ShapeCastable, ShapeLike
+from ._ast import Value, ValueCastable, ValueLike
+from ._ast import Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal
+from ._dsl import SyntaxError, SyntaxWarning, Module
+from ._cd import DomainError, ClockDomain
+from ._ir import UnusedElaboratable, Elaboratable, DriverConflict, Fragment, Instance
+from ._mem import Memory, ReadPort, WritePort, DummyPort
+from ._rec import Record
+from ._xfrm import DomainRenamer, ResetInserter, EnableInserter
 
 
 __all__ = [
-    "Shape", "unsigned", "signed",
-    "Value", "Const", "C", "Mux", "Cat", "Repl", "Array", "Signal", "ClockSignal", "ResetSignal",
-    "Module",
-    "ClockDomain",
-    "Elaboratable", "Fragment", "Instance",
-    "Memory",
+    # _ast
+    "Shape", "unsigned", "signed", "ShapeCastable", "ShapeLike",
+    "Value", "ValueCastable", "ValueLike",
+    "Const", "C", "Mux", "Cat", "Repl", "Array", "Signal", "ClockSignal", "ResetSignal",
+    # _dsl
+    "SyntaxError", "SyntaxWarning", "Module",
+    # _cd
+    "DomainError", "ClockDomain",
+    # _ir
+    "UnusedElaboratable", "Elaboratable", "DriverConflict", "Fragment", "Instance",
+    # _mem
+    "Memory", "ReadPort", "WritePort", "DummyPort",
+    # _rec
     "Record",
+    # _xfrm
     "DomainRenamer", "ResetInserter", "EnableInserter",
 ]

amaranth/hdl/__init__.py

@@ -1,5 +1,5 @@
 from .. import tracer
-from .ast import Signal
+from ._ast import Signal
 
 
 __all__ = ["ClockDomain", "DomainError"]

amaranth/hdl/_cd.py

@@ -8,10 +8,10 @@
 from .._utils import flatten
 from ..utils import bits_for
 from .. import tracer
-from .ast import *
-from .ir import *
-from .cd import *
-from .xfrm import *
+from ._ast import *
+from ._ir import *
+from ._cd import *
+from ._xfrm import *
 
 
 __all__ = ["SyntaxError", "SyntaxWarning", "Module"]

amaranth/hdl/_dsl.py

@@ -6,8 +6,8 @@
 from .. import tracer
 from .._utils import *
 from .._unused import *
-from .ast import *
-from .cd import *
+from ._ast import *
+from ._cd import *
 
 
 __all__ = ["UnusedElaboratable", "Elaboratable", "DriverConflict", "Fragment", "Instance"]
@@ -263,7 +263,7 @@ def flatten_subfrags_if_needed(subfrags):
         return SignalSet(driver_subfrags.keys())
 
     def _propagate_domains_up(self, hierarchy=("top",)):
-        from .xfrm import DomainRenamer
+        from ._xfrm import DomainRenamer
 
         domain_subfrags = defaultdict(set)
 
@@ -327,7 +327,7 @@ def _propagate_domains_down(self):
             subfrag._propagate_domains_down()
 
     def _create_missing_domains(self, missing_domain, *, platform=None):
-        from .xfrm import DomainCollector
+        from ._xfrm import DomainCollector
 
         collector = DomainCollector()
         collector(self)
@@ -507,7 +507,7 @@ def lca_of(fragu, fragv):
                 self.add_ports(sig, dir="i")
 
     def prepare(self, ports=None, missing_domain=lambda name: ClockDomain(name)):
-        from .xfrm import DomainLowerer
+        from ._xfrm import DomainLowerer
 
         new_domains = self._propagate_domains(missing_domain)
         fragment = DomainLowerer()(self)