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rroohhhwhitequark
rroohhh
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whitequark
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test: make nmigen 0.3+ compatible
and bump minimum nmigen version to 0.2
1 parent 1218e26 commit c754caf

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6 files changed

+56
-41
lines changed

6 files changed

+56
-41
lines changed

‎nmigen_soc/test/test_csr_bus.py‎

Lines changed: 12 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -240,9 +240,10 @@ def sim_test():
240240
self.assertEqual((yield elem_16_rw.w_stb), 1)
241241
self.assertEqual((yield elem_16_rw.w_data), 0xaa55)
242242

243-
with Simulator(self.dut, vcd_file=open("test.vcd", "w")) as sim:
244-
sim.add_clock(1e-6)
245-
sim.add_sync_process(sim_test())
243+
sim = Simulator(self.dut)
244+
sim.add_clock(1e-6)
245+
sim.add_sync_process(sim_test)
246+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
246247
sim.run()
247248

248249

@@ -299,9 +300,10 @@ def sim_test():
299300
self.assertEqual((yield elem_20_rw.w_stb), 1)
300301
self.assertEqual((yield elem_20_rw.w_data), 0x3aa55)
301302

302-
with Simulator(self.dut, vcd_file=open("test.vcd", "w")) as sim:
303-
sim.add_clock(1e-6)
304-
sim.add_sync_process(sim_test())
303+
sim = Simulator(self.dut)
304+
sim.add_clock(1e-6)
305+
sim.add_sync_process(sim_test)
306+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
305307
sim.run()
306308

307309

@@ -398,7 +400,8 @@ def sim_test():
398400

399401
m = Module()
400402
m.submodules += self.dut, mux_1, mux_2
401-
with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
402-
sim.add_clock(1e-6)
403-
sim.add_sync_process(sim_test())
403+
sim = Simulator(m)
404+
sim.add_clock(1e-6)
405+
sim.add_sync_process(sim_test)
406+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
404407
sim.run()

‎nmigen_soc/test/test_csr_event.py‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,10 @@
99

1010

1111
def simulation_test(dut, process):
12-
with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
13-
sim.add_clock(1e-6)
14-
sim.add_sync_process(process)
12+
sim = Simulator(dut)
13+
sim.add_clock(1e-6)
14+
sim.add_sync_process(process)
15+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
1516
sim.run()
1617

1718

‎nmigen_soc/test/test_csr_wishbone.py‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -135,9 +135,10 @@ def sim_test():
135135

136136
m = Module()
137137
m.submodules += mux, reg_1, reg_2, dut
138-
with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
139-
sim.add_clock(1e-6)
140-
sim.add_sync_process(sim_test())
138+
sim = Simulator(m)
139+
sim.add_clock(1e-6)
140+
sim.add_sync_process(sim_test)
141+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
141142
sim.run()
142143

143144
def test_wide(self):
@@ -222,7 +223,8 @@ def sim_test():
222223

223224
m = Module()
224225
m.submodules += mux, reg, dut
225-
with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
226-
sim.add_clock(1e-6)
227-
sim.add_sync_process(sim_test())
226+
sim = Simulator(m)
227+
sim.add_clock(1e-6)
228+
sim.add_sync_process(sim_test)
229+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
228230
sim.run()

‎nmigen_soc/test/test_event.py‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,10 @@
88

99

1010
def simulation_test(dut, process):
11-
with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
12-
sim.add_clock(1e-6)
13-
sim.add_sync_process(process)
11+
sim = Simulator(dut)
12+
sim.add_clock(1e-6)
13+
sim.add_sync_process(process)
14+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
1415
sim.run()
1516

1617

‎nmigen_soc/test/test_wishbone_bus.py‎

Lines changed: 27 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -238,8 +238,9 @@ def sim_test():
238238
self.assertEqual((yield dut.bus.stall), 1)
239239
self.assertEqual((yield dut.bus.dat_r), 0x5678abcd)
240240

241-
with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
242-
sim.add_process(sim_test())
241+
sim = Simulator(dut)
242+
sim.add_process(sim_test)
243+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
243244
sim.run()
244245

245246
def test_addr_translate(self):
@@ -348,8 +349,9 @@ def sim_test():
348349

349350
m = Module()
350351
m.submodules += dut, loop_1, loop_2, loop_3, loop_4
351-
with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
352-
sim.add_process(sim_test())
352+
sim = Simulator(m)
353+
sim.add_process(sim_test)
354+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
353355
sim.run()
354356

355357
def test_coarse_granularity(self):
@@ -369,8 +371,9 @@ def sim_test():
369371
yield Delay(1e-6)
370372
self.assertEqual((yield sub.cyc), 0)
371373

372-
with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
373-
sim.add_process(sim_test())
374+
sim = Simulator(dut)
375+
sim.add_process(sim_test)
376+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
374377
sim.run()
375378

376379

@@ -475,9 +478,10 @@ def sim_test():
475478
self.assertEqual((yield intr_2.rty), 1)
476479
self.assertEqual((yield intr_2.stall), 0)
477480

478-
with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
479-
sim.add_clock(1e-6)
480-
sim.add_sync_process(sim_test())
481+
sim = Simulator(dut)
482+
sim.add_clock(1e-6)
483+
sim.add_sync_process(sim_test)
484+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
481485
sim.run()
482486

483487
def test_lock(self):
@@ -526,9 +530,10 @@ def sim_test():
526530
self.assertEqual((yield intr_1.ack), 0)
527531
self.assertEqual((yield intr_2.ack), 1)
528532

529-
with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
530-
sim.add_clock(1e-6)
531-
sim.add_sync_process(sim_test())
533+
sim = Simulator(dut)
534+
sim.add_clock(1e-6)
535+
sim.add_sync_process(sim_test)
536+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
532537
sim.run()
533538

534539
def test_stall(self):
@@ -551,8 +556,9 @@ def sim_test():
551556
self.assertEqual((yield intr_1.stall), 1)
552557
self.assertEqual((yield intr_2.stall), 1)
553558

554-
with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
555-
sim.add_process(sim_test())
559+
sim = Simulator(dut)
560+
sim.add_process(sim_test)
561+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
556562
sim.run()
557563

558564
def test_stall_compat(self):
@@ -574,8 +580,9 @@ def sim_test():
574580
self.assertEqual((yield intr_1.stall), 0)
575581
self.assertEqual((yield intr_2.stall), 1)
576582

577-
with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
578-
sim.add_process(sim_test())
583+
sim = Simulator(dut)
584+
sim.add_process(sim_test)
585+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
579586
sim.run()
580587

581588
def test_roundrobin(self):
@@ -633,7 +640,8 @@ def sim_test():
633640
self.assertEqual((yield intr_2.ack), 0)
634641
self.assertEqual((yield intr_3.ack), 1)
635642

636-
with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
637-
sim.add_clock(1e-6)
638-
sim.add_sync_process(sim_test())
643+
sim = Simulator(dut)
644+
sim.add_clock(1e-6)
645+
sim.add_sync_process(sim_test)
646+
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
639647
sim.run()

‎setup.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ def local_scheme(version):
2323
#long_description="""TODO""",
2424
license="BSD",
2525
setup_requires=["wheel", "setuptools", "setuptools_scm"],
26-
install_requires=["nmigen>=0.1,<0.5"],
26+
install_requires=["nmigen>=0.2,<0.5"],
2727
packages=find_packages(),
2828
project_urls={
2929
"Source Code": "https://github.com/nmigen/nmigen-soc",

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