csr: update for RFC 43, rename reset= to init=.

Author: wanda-phi

amaranth_soc/csr/action.py

@@ -81,8 +81,8 @@ class RW(FieldAction):
     ----------
     shape : :ref:`shape-castable <lang-shapecasting>`
         Shape of the field.
-    reset : :class:`int`
-        Storage reset value.
+    init : :class:`int`
+        Storage initial value.
 
     Interface attributes
     --------------------
@@ -91,16 +91,16 @@ class RW(FieldAction):
     data : Signal(shape)
         Storage output.
     """
-    def __init__(self, shape, *, reset=0):
+    def __init__(self, shape, *, init=0):
         super().__init__(shape, access="rw", members={
             "data": Out(shape),
         })
-        self._storage = Signal(shape, reset=reset)
-        self._reset   = reset
+        self._storage = Signal(shape, init=init)
+        self._init    = init
 
     @property
-    def reset(self):
-        return self._reset
+    def init(self):
+        return self._init
 
     def elaborate(self, platform):
         m = Module()
@@ -129,8 +129,8 @@ class RW1C(FieldAction):
     ----------
     shape : :ref:`shape-castable <lang-shapecasting>`
         Shape of the field.
-    reset : :class:`int`
-        Storage reset value.
+    init : :class:`int`
+        Storage initial value.
 
     Interface attributes
     --------------------
@@ -141,17 +141,17 @@ class RW1C(FieldAction):
     set : Signal(shape)
         Mask to set storage bits.
     """
-    def __init__(self, shape, *, reset=0):
+    def __init__(self, shape, *, init=0):
         super().__init__(shape, access="rw", members={
             "data": Out(shape),
             "set":  In(shape),
         })
-        self._storage = Signal(shape, reset=reset)
-        self._reset   = reset
+        self._storage = Signal(shape, init=init)
+        self._init    = init
 
     @property
-    def reset(self):
-        return self._reset
+    def init(self):
+        return self._init
 
     def elaborate(self, platform):
         m = Module()
@@ -183,8 +183,8 @@ class RW1S(FieldAction):
     ----------
     shape : :ref:`shape-castable <lang-shapecasting>`
         Shape of the field.
-    reset : :class:`int`
-        Storage reset value.
+    init : :class:`int`
+        Storage initial value.
 
     Interface attributes
     --------------------
@@ -195,17 +195,17 @@ class RW1S(FieldAction):
     clear : Signal(shape)
         Mask to clear storage bits.
     """
-    def __init__(self, shape, *, reset=0):
+    def __init__(self, shape, *, init=0):
         super().__init__(shape, access="rw", members={
             "clear": In(shape),
             "data":  Out(shape),
         })
-        self._storage = Signal(shape, reset=reset)
-        self._reset   = reset
+        self._storage = Signal(shape, init=init)
+        self._init    = init
 
     @property
-    def reset(self):
-        return self._reset
+    def init(self):
+        return self._init
 
     def elaborate(self, platform):
         m = Module()

amaranth_soc/wishbone/bus.py

@@ -501,7 +501,7 @@ def elaborate(self, platform):
             for i, intr_bus in enumerate(self._intrs):
                 m.d.comb += intr_bus.dat_r.eq(self.bus.dat_r)
                 if hasattr(intr_bus, "stall"):
-                    intr_bus_stall = Signal(reset=1)
+                    intr_bus_stall = Signal(init=1)
                     m.d.comb += intr_bus.stall.eq(intr_bus_stall)
 
                 with m.Case(i):

tests/test_csr_action.py

@@ -55,20 +55,20 @@ def process():
 
 class RWTestCase(unittest.TestCase):
     def test_simple(self):
-        f4 = action.RW(unsigned(4), reset=0x5)
+        f4 = action.RW(unsigned(4), init=0x5)
         self.assertEqual(f4.data.shape(), unsigned(4))
-        self.assertEqual(f4.reset, 0x5)
+        self.assertEqual(f4.init, 0x5)
         self.assertTrue(f4.port.access.readable())
         self.assertTrue(f4.port.access.writable())
 
         f8 = action.RW(signed(8))
         self.assertEqual(f8.data.shape(), signed(8))
-        self.assertEqual(f8.reset, 0)
+        self.assertEqual(f8.init, 0)
         self.assertTrue(f8.port.access.readable())
         self.assertTrue(f8.port.access.writable())
 
     def test_sim(self):
-        dut = action.RW(unsigned(4), reset=0x5)
+        dut = action.RW(unsigned(4), init=0x5)
 
         def process():
             self.assertEqual((yield dut.port.r_data), 0x5)
@@ -88,22 +88,22 @@ def process():
 
 class RW1CTestCase(unittest.TestCase):
     def test_simple(self):
-        f4 = action.RW1C(unsigned(4), reset=0x5)
+        f4 = action.RW1C(unsigned(4), init=0x5)
         self.assertEqual(f4.data.shape(), unsigned(4))
         self.assertEqual(f4.set .shape(), unsigned(4))
-        self.assertEqual(f4.reset, 0x5)
+        self.assertEqual(f4.init, 0x5)
         self.assertTrue(f4.port.access.readable())
         self.assertTrue(f4.port.access.writable())
 
         f8 = action.RW1C(signed(8))
         self.assertEqual(f8.data.shape(), signed(8))
         self.assertEqual(f8.set .shape(), signed(8))
-        self.assertEqual(f8.reset, 0)
+        self.assertEqual(f8.init, 0)
         self.assertTrue(f8.port.access.readable())
         self.assertTrue(f8.port.access.writable())
 
     def test_sim(self):
-        dut = action.RW1C(unsigned(4), reset=0xf)
+        dut = action.RW1C(unsigned(4), init=0xf)
 
         def process():
             self.assertEqual((yield dut.port.r_data), 0xf)
@@ -129,22 +129,22 @@ def process():
 
 class RW1STestCase(unittest.TestCase):
     def test_simple(self):
-        f4 = action.RW1S(unsigned(4), reset=0x5)
+        f4 = action.RW1S(unsigned(4), init=0x5)
         self.assertEqual(f4.data .shape(), unsigned(4))
         self.assertEqual(f4.clear.shape(), unsigned(4))
-        self.assertEqual(f4.reset, 0x5)
+        self.assertEqual(f4.init, 0x5)
         self.assertTrue(f4.port.access.readable())
         self.assertTrue(f4.port.access.writable())
 
         f8 = action.RW1S(signed(8))
         self.assertEqual(f8.data .shape(), signed(8))
         self.assertEqual(f8.clear.shape(), signed(8))
-        self.assertEqual(f8.reset, 0)
+        self.assertEqual(f8.init, 0)
         self.assertTrue(f8.port.access.readable())
         self.assertTrue(f8.port.access.writable())
 
     def test_sim(self):
-        dut = action.RW1S(unsigned(4), reset=0x5)
+        dut = action.RW1S(unsigned(4), init=0x5)
 
         def process():
             self.assertEqual((yield dut.port.r_data), 0x5)

tests/test_csr_reg.py

@@ -141,18 +141,18 @@ class Foo:
 
     def test_create(self):
         class MockAction(FieldAction):
-            def __init__(self, shape, *, reset):
+            def __init__(self, shape, *, init):
                 super().__init__(shape, access="rw", members={
                     "data": Out(shape)
                 })
-                self.reset = reset
+                self.init = init
 
             def elaborate(self, platform):
                 return Module()
 
-        field_u8 = Field(MockAction, unsigned(8), reset=1).create()
+        field_u8 = Field(MockAction, unsigned(8), init=1).create()
         self.assertEqual(field_u8.port.shape, unsigned(8))
-        self.assertEqual(field_u8.reset, 1)
+        self.assertEqual(field_u8.init, 1)
 
     def test_create_multiple(self):
         class MockAction(FieldAction):
@@ -500,15 +500,15 @@ class FooRegister(Register, access="rw"):
     def test_sim(self):
         class FooRegister(Register, access="rw"):
             a: Field(action.R, unsigned(1))
-            b: Field(action.RW1C, unsigned(3), reset=0b111)
-            c: {"d": Field(action.RW, signed(2), reset=-1)}
+            b: Field(action.RW1C, unsigned(3), init=0b111)
+            c: {"d": Field(action.RW, signed(2), init=-1)}
             e: [Field(action.W, unsigned(1)) for _ in range(2)]
             f: Field(action.RW1S, unsigned(3))
 
         dut = FooRegister()
 
         def process():
-            # Check reset values:
+            # Check init values:
 
             self.assertEqual((yield dut.f.b  .data),  0b111)
             self.assertEqual((yield dut.f.c.d.data), -1)
@@ -888,8 +888,8 @@ def test_memory_map_name_conflicts(self):
 
 class BridgeTestCase(unittest.TestCase):
     class _RWRegister(Register, access="rw"):
-        def __init__(self, width, reset=0):
-            super().__init__({"a": Field(action.RW, width, reset=reset)})
+        def __init__(self, width, init=0):
+            super().__init__({"a": Field(action.RW, width, init=init)})
 
     def test_wrong_memory_map(self):
         with self.assertRaisesRegex(TypeError,
@@ -917,10 +917,10 @@ def __repr__(self):
     def test_sim(self):
         regs = Builder(addr_width=16, data_width=8)
 
-        reg_rw_4 = regs.add("reg_rw_4", self._RWRegister(4, reset=0x0))
-        reg_rw_8 = regs.add("reg_rw_8", self._RWRegister(8, reset=0x11))
+        reg_rw_4 = regs.add("reg_rw_4", self._RWRegister(4, init=0x0))
+        reg_rw_8 = regs.add("reg_rw_8", self._RWRegister(8, init=0x11))
         with regs.Cluster("cluster_0"):
-            reg_rw_16 = regs.add("reg_rw_16", self._RWRegister(16, reset=0x3322))
+            reg_rw_16 = regs.add("reg_rw_16", self._RWRegister(16, init=0x3322))
 
         dut = Bridge(regs.as_memory_map())