@@ -330,14 +330,8 @@ def add(self, sub_bus, *, addr=None):
330330 raise ValueError ("Subordinate bus has data width {}, which is not the same as "
331331 "multiplexer data width {}"
332332 .format (sub_bus .data_width , self .bus .data_width ))
333-
334- start , end , ratio = window_range = self ._map .add_window (sub_bus .memory_map , addr = addr )
335- assert ratio == 1
336- pattern = "{:0{}b}{}" .format (start >> sub_bus .addr_width ,
337- self .bus .addr_width - sub_bus .addr_width ,
338- "-" * sub_bus .addr_width )
339- self ._subs [pattern ] = sub_bus
340- return window_range
333+ self ._subs [sub_bus .memory_map ] = sub_bus
334+ return self ._map .add_window (sub_bus .memory_map , addr = addr )
341335
342336 def elaborate (self , platform ):
343337 m = Module ()
@@ -346,7 +340,8 @@ def elaborate(self, platform):
346340 r_data_fanin = 0
347341
348342 with m .Switch (self .bus .addr ):
349- for sub_pat , sub_bus in self ._subs .items ():
343+ for sub_map , sub_pat in self ._map .window_patterns ():
344+ sub_bus = self ._subs [sub_map ]
350345 m .d .comb += sub_bus .addr .eq (self .bus .addr [:sub_bus .addr_width ])
351346
352347 # The CSR bus interface is defined to output zero when idle, allowing us to avoid
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