fix autodoc import paths

Author: jfng

amaranth_soc/csr/action.py

@@ -8,7 +8,7 @@
 
 
 class R(FieldAction):
-    """A read-only :class:`FieldAction`.
+    """A read-only :class:`.FieldAction`.
 
     Arguments
     ---------
@@ -17,12 +17,12 @@ class R(FieldAction):
 
     Attributes
     ----------
-    port : :class:`FieldPort`
+    port : :class:`.FieldPort`
         Field port.
     r_data : :pc:`unsigned(shape)`
-        Read data. Drives ``port.r_data``. See :class:`FieldPort`.
+        Read data. Drives ``port.r_data``. See :class:`.FieldPort`.
     r_stb : :pc:`unsigned(data)`
-        Read strobe. Driven by ``port.r_stb``. See :class:`FieldPort`.
+        Read strobe. Driven by ``port.r_stb``. See :class:`.FieldPort`.
     """
     def __init__(self, shape):
         super().__init__(shape, access="r", members={
@@ -40,7 +40,7 @@ def elaborate(self, platform):
 
 
 class W(FieldAction):
-    """A write-only :class:`FieldAction`.
+    """A write-only :class:`.FieldAction`.
 
     Arguments
     ---------
@@ -49,12 +49,12 @@ class W(FieldAction):
 
     Attributes
     ----------
-    port : :class:`FieldPort`
+    port : :class:`.FieldPort`
         Field port.
     w_data : :pc:`unsigned(shape)`
-        Write data. Driven by ``port.w_data``. See :class:`FieldPort`.
+        Write data. Driven by ``port.w_data``. See :class:`.FieldPort`.
     w_stb : :pc:`unsigned(shape)`
-        Write strobe. Driven by ``port.w_stb``. See :class:`FieldPort`.
+        Write strobe. Driven by ``port.w_stb``. See :class:`.FieldPort`.
     """
     def __init__(self, shape):
         super().__init__(shape, access="w", members={
@@ -72,7 +72,7 @@ def elaborate(self, platform):
 
 
 class RW(FieldAction):
-    """A read/write :class:`FieldAction`, with built-in storage.
+    """A read/write :class:`.FieldAction`, with built-in storage.
 
     Storage is updated with the value of ``port.w_data`` one clock cycle after ``port.w_stb`` is
     asserted.
@@ -86,7 +86,7 @@ class RW(FieldAction):
 
     Attributes
     ----------
-    port : :class:`FieldPort`
+    port : :class:`.FieldPort`
         Field port.
     data : :pc:`unsigned(shape)`
         Storage output.
@@ -123,7 +123,7 @@ def elaborate(self, platform):
 
 
 class RW1C(FieldAction):
-    """A read/write-one-to-clear :class:`FieldAction`, with built-in storage.
+    """A read/write-one-to-clear :class:`.FieldAction`, with built-in storage.
 
     Storage bits are:
 
@@ -141,7 +141,7 @@ class RW1C(FieldAction):
 
     Attributes
     ----------
-    port : :class:`FieldPort`
+    port : :class:`.FieldPort`
         Field port.
     data : :pc:`unsigned(shape)`
         Storage output.
@@ -184,7 +184,7 @@ def elaborate(self, platform):
 
 
 class RW1S(FieldAction):
-    """A read/write-one-to-set :class:`FieldAction`, with built-in storage.
+    """A read/write-one-to-set :class:`.FieldAction`, with built-in storage.
 
     Storage bits are:
 
@@ -202,7 +202,7 @@ class RW1S(FieldAction):
 
     Attributes
     ----------
-    port : :class:`FieldPort`
+    port : :class:`.FieldPort`
         Field port.
     data : :pc:`unsigned(shape)`
         Storage output.
@@ -255,7 +255,7 @@ class _Reserved(FieldAction):
 
     Attributes
     ----------
-    port : :class:`FieldPort`
+    port : :class:`.FieldPort`
         Field port.
     """
     def __init__(self, shape):
@@ -267,23 +267,23 @@ def elaborate(self, platform):
 
 class ResRAW0(_Reserved):
     __doc__ = _Reserved._doc_template.format(description="""
-    A reserved read-any/write-zero :class:`FieldAction`.
+    A reserved read-any/write-zero :class:`.FieldAction`.
     """)
 
 
 class ResRAWL(_Reserved):
     __doc__ = _Reserved._doc_template.format(description="""
-    A reserved read-any/write-last :class:`FieldAction`.
+    A reserved read-any/write-last :class:`.FieldAction`.
     """)
 
 
 class ResR0WA(_Reserved):
     __doc__ = _Reserved._doc_template.format(description="""
-    A reserved read-zero/write-any :class:`FieldAction`.
+    A reserved read-zero/write-any :class:`.FieldAction`.
     """)
 
 
 class ResR0W0(_Reserved):
     __doc__ = _Reserved._doc_template.format(description="""
-    A reserved read-zero/write-zero :class:`FieldAction`.
+    A reserved read-zero/write-zero :class:`.FieldAction`.
     """)

amaranth_soc/csr/bus.py

@@ -71,7 +71,7 @@ class Signature(wiring.Signature):
         ---------
         width : :class:`int`
             Width of the register.
-        access : :class:`Access`
+        access : :class:`Element.Access`
             Register access mode.
 
         Attributes
@@ -384,7 +384,7 @@ def memory_map(self):
 
         Returns
         -------
-        :class:`MemoryMap` or ``None``
+        :class:`.MemoryMap` or ``None``
         """
         if self._memory_map is None:
             raise AttributeError(f"{self!r} does not have a memory map")
@@ -447,7 +447,7 @@ class Multiplexer(wiring.Component):
 
     Arguments
     ---------
-    memory_map : :class:`..memory.MemoryMap`
+    memory_map : :class:`.MemoryMap`
         Memory map of CSR registers.
     shadow_overlaps : :class:`int`
         Maximum number of CSR registers that can share a chunk of a shadow register.
@@ -755,9 +755,9 @@ class Decoder(wiring.Component):
     data_width : :class:`int`
         Data width. See :class:`Interface`.
     alignment : :class:`int`, power-of-2 exponent
-        Window alignment. See :class:`..memory.MemoryMap`.
+        Window alignment. See :class:`.MemoryMap`.
     name : :class:`str`
-        Window name. Optional. See :class:`..memory.MemoryMap`.
+        Window name. Optional. See :class:`.MemoryMap`.
 
     Attributes
     ----------
@@ -773,7 +773,7 @@ def __init__(self, *, addr_width, data_width, alignment=0, name=None):
     def align_to(self, alignment):
         """Align the implicit address of the next window.
 
-        See :meth:`MemoryMap.align_to` for details.
+        See :meth:`.MemoryMap.align_to` for details.
 
         Returns
         -------
@@ -785,9 +785,9 @@ def align_to(self, alignment):
     def add(self, sub_bus, *, addr=None):
         """Add a window to a subordinate bus.
 
-        See :meth:`MemoryMap.add_window` for details.
+        See :meth:`.MemoryMap.add_window` for details.
 
-        .. todo:: include exceptions raised in :meth:`MemoryMap.add_window`
+        .. todo:: include exceptions raised in :meth:`.MemoryMap.add_window`
 
         Returns
         -------

amaranth_soc/csr/reg.py

@@ -287,7 +287,7 @@ class FieldActionMap(Mapping):
 
           - a :class:`Field` is instantiated as a :class:`FieldAction` (see :meth:`Field.create`);
           - a :class:`dict` is instantiated as a :class:`FieldActionMap`;
-          - a :class:`list` is instantiated as a :class:`FieldArrayMap`.
+          - a :class:`list` is instantiated as a :class:`FieldActionArray`.
 
     Raises
     ------
@@ -386,7 +386,7 @@ def flatten(self):
 
         Yields
         ------
-        iter(:class:`str`)
+        iterable of :class:`str`
             Path of the field. It is prefixed by the name of every nested :class:`FieldActionMap`
             or :class:`FieldActionArray`.
         :class:`FieldAction`
@@ -410,7 +410,7 @@ class FieldActionArray(Sequence):
 
           - a :class:`Field` is instantiated as a :class:`FieldAction` (see :meth:`Field.create`);
           - a :class:`dict` is instantiated as a :class:`FieldActionMap`;
-          - a :class:`list` is instantiated as a :class:`FieldArrayMap`.
+          - a :class:`list` is instantiated as a :class:`FieldActionArray`.
 
     Raises
     ------
@@ -464,7 +464,7 @@ def flatten(self):
 
         Yields
         ------
-        iter(:class:`str`)
+        iterable of :class:`str`
             Path of the field. It is prefixed by the name of every nested :class:`FieldActionMap`
             or :class:`FieldActionArray`.
         :class:`FieldAction`
@@ -856,13 +856,13 @@ def Index(self, index):
             assert self._scope_stack.pop() == index
 
     def as_memory_map(self):
-        """Build a :class:`MemoryMap`.
+        """Build a :class:`.MemoryMap`.
 
         .. todo:: explain address/offset conversions
 
         Returns
         -------
-        :class:`MemoryMap`.
+        :class:`.MemoryMap`.
         """
         self.freeze()
         memory_map = MemoryMap(addr_width=self.addr_width, data_width=self.data_width,
@@ -888,18 +888,18 @@ class Bridge(wiring.Component):
 
     Arguments
     ---------
-    memory_map : :class:`MemoryMap`
+    memory_map : :class:`.MemoryMap`
         Memory map of CSR registers.
 
     Attributes
     ----------
-    bus : :class:`Interface`
+    bus : :class:`.Interface`
         CSR bus providing access to the contents of ``memory_map``.
 
     Raises
     ------
     :exc:`TypeError`
-        If ``memory_map`` is not a :class:`MemoryMap` object.
+        If ``memory_map`` is not a :class:`.MemoryMap` object.
     :exc:`ValueError`
         If ``memory_map`` has windows.
     :exc:`TypeError`

amaranth_soc/wishbone/bus.py

@@ -246,7 +246,7 @@ class Interface(wiring.PureInterface):
 
     .. note::
 
-        The data width of the underlying :class:`MemoryMap` of the interface is equal to port
+        The data width of the underlying :class:`.MemoryMap` of the interface is equal to port
         granularity, not port size. If port granularity is less than port size, then the address
         width of the underlying memory map is extended to reflect that.
 
@@ -331,7 +331,7 @@ def memory_map(self):
 
         Returns
         -------
-        :class:`MemoryMap` or ``None``
+        :class:`.MemoryMap` or ``None``
         """
         if self._memory_map is None:
             raise AttributeError(f"{self!r} does not have a memory map")
@@ -373,9 +373,9 @@ class Decoder(wiring.Component):
     features : iterable of :class:`Feature`
         Optional signal set. See :class:`Signature`.
     alignment : :class:`int`, power-of-2 exponent
-        Window alignment. Optional. See :class:`~..memory.MemoryMap`.
+        Window alignment. Optional. See :class:`.MemoryMap`.
     name : :class:`str`
-        Window name. Optional. See :class:`~..memory.MemoryMap`.
+        Window name. Optional. See :class:`.MemoryMap`.
 
     Attributes
     ----------
@@ -396,7 +396,7 @@ def __init__(self, *, addr_width, data_width, granularity=None, features=frozens
     def align_to(self, alignment):
         """Align the implicit address of the next window.
 
-        See :meth:`MemoryMap.align_to` for details.
+        See :meth:`.MemoryMap.align_to` for details.
 
         Returns
         -------
@@ -408,7 +408,7 @@ def align_to(self, alignment):
     def add(self, sub_bus, *, addr=None, sparse=False):
         """Add a window to a subordinate bus.
 
-        See :meth:`MemoryMap.add_window` for details.
+        See :meth:`.MemoryMap.add_window` for details.
 
         .. note::
 
@@ -422,7 +422,7 @@ def add(self, sub_bus, *, addr=None, sparse=False):
             In either case, the granularity of the subordinate bus must be equal to or less than
             the granularity of the :class:`Decoder`.
 
-        .. todo:: include exceptions raised in :meth:`MemoryMap.add_window`
+        .. todo:: include exceptions raised in :meth:`.MemoryMap.add_window`
 
         Returns
         -------