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jfngjfng
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Remove use of deprecated log2_int function.
See amaranth-lang/rfcs#17.
1 parent 87ee8a5 commit 2f2ad5c

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4 files changed

+21
-20
lines changed

4 files changed

+21
-20
lines changed

‎amaranth_soc/csr/bus.py‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
from amaranth import *
33
from amaranth.lib import enum, wiring
44
from amaranth.lib.wiring import In, Out, flipped
5-
from amaranth.utils import log2_int
5+
from amaranth.utils import ceil_log2
66

77
from ..memory import MemoryMap
88

@@ -384,13 +384,13 @@ def add(self, elem_range):
384384
Arguments
385385
---------
386386
elem_range : :class:`range`
387-
Address range of a CSR :class:`Element`. It uses ``2 ** ceil(log2(elem_range.stop -
388-
elem_range.start))`` chunks of the shadow register. If this amount is greater than
387+
Address range of a CSR :class:`Element`. It uses ``2 ** ceil_log2(elem_range.stop -
388+
elem_range.start)`` chunks of the shadow register. If this amount is greater than
389389
:attr:`~Multiplexer._Shadow.size`, it replaces the latter.
390390
"""
391391
assert isinstance(elem_range, range)
392392
self._ranges.add(elem_range)
393-
elem_size = 2 ** log2_int(elem_range.stop - elem_range.start, need_pow2=False)
393+
elem_size = 2 ** ceil_log2(elem_range.stop - elem_range.start)
394394
self._size = max(self._size, elem_size)
395395

396396
def decode_address(self, addr, elem_range):
@@ -415,7 +415,7 @@ def decode_address(self, addr, elem_range):
415415
|0001|11|00|
416416
+----+--+--+
417417
│ └─ 0
418-
└──── ceil(log2(elem_range.stop - elem_range.start))
418+
└──── ceil_log2(elem_range.stop - elem_range.start)
419419
420420
The upper bits of the offset would be ``0b10``, extracted from ``elem_range.start``:
421421
@@ -425,13 +425,13 @@ def decode_address(self, addr, elem_range):
425425
|0001|10|11|
426426
+----+--+--+
427427
│ │
428-
│ └──── ceil(log2(elem_range.stop - elem_range.start))
428+
│ └──── ceil_log2(elem_range.stop - elem_range.start)
429429
└─────── log2(self.size)
430430
431431
The decoded offset would therefore be ``8`` (i.e. ``0b1000``).
432432
"""
433433
assert elem_range in self._ranges and addr in elem_range
434-
elem_size = 2 ** log2_int(elem_range.stop - elem_range.start, need_pow2=False)
434+
elem_size = 2 ** ceil_log2(elem_range.stop - elem_range.start)
435435
self_mask = self.size - 1
436436
elem_mask = elem_size - 1
437437
return elem_range.start & self_mask & ~elem_mask | addr & elem_mask
@@ -446,7 +446,7 @@ def encode_offset(self, offset, elem_range):
446446
located at ``offset``. See :meth:`~Multiplexer._Shadow.decode_address` for details.
447447
"""
448448
assert elem_range in self._ranges and isinstance(offset, int)
449-
elem_size = 2 ** log2_int(elem_range.stop - elem_range.start, need_pow2=False)
449+
elem_size = 2 ** ceil_log2(elem_range.stop - elem_range.start)
450450
return elem_range.start + ((offset - elem_range.start) % elem_size)
451451

452452
def prepare(self):

‎amaranth_soc/csr/event.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
from amaranth import *
55
from amaranth.lib import wiring
66
from amaranth.lib.wiring import In, Out, flipped, connect
7-
from amaranth.utils import log2_int
7+
from amaranth.utils import ceil_log2
88

99
from . import Element, Multiplexer
1010
from .. import event
@@ -58,7 +58,7 @@ def __init__(self, event_map, *, trigger="level", data_width, alignment=0, name=
5858
self._pending = Element(event_map.size, "rw")
5959

6060
elem_size = ceil(event_map.size / data_width)
61-
addr_width = 1 + max(log2_int(elem_size, need_pow2=False), alignment)
61+
addr_width = 1 + max(ceil_log2(elem_size), alignment)
6262
self._mux = Multiplexer(addr_width=addr_width, data_width=data_width,
6363
alignment=alignment)
6464
self._mux.add(self._enable, name="enable")

‎amaranth_soc/csr/wishbone.py‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
from amaranth import *
22
from amaranth.lib import wiring
33
from amaranth.lib.wiring import In, flipped
4-
from amaranth.utils import log2_int
4+
from amaranth.utils import exact_log2
55

66
from . import Interface
77
from .. import wishbone
@@ -51,9 +51,10 @@ def __init__(self, csr_bus, *, data_width=None, name=None):
5151
if data_width is None:
5252
data_width = csr_bus.data_width
5353

54-
wb_sig = wishbone.Signature(addr_width=max(0, csr_bus.addr_width -
55-
log2_int(data_width // csr_bus.data_width)),
56-
data_width=data_width, granularity=csr_bus.data_width)
54+
ratio = data_width // csr_bus.data_width
55+
wb_sig = wishbone.Signature(addr_width=max(0, csr_bus.addr_width - exact_log2(ratio)),
56+
data_width=data_width,
57+
granularity=csr_bus.data_width)
5758

5859
super().__init__({"wb_bus": In(wb_sig)})
5960

@@ -76,7 +77,7 @@ def elaborate(self, platform):
7677
m = Module()
7778

7879
cycle = Signal(range(len(wb_bus.sel) + 1))
79-
m.d.comb += csr_bus.addr.eq(Cat(cycle[:log2_int(len(wb_bus.sel))], wb_bus.adr))
80+
m.d.comb += csr_bus.addr.eq(Cat(cycle[:exact_log2(len(wb_bus.sel))], wb_bus.adr))
8081

8182
with m.If(wb_bus.cyc & wb_bus.stb):
8283
with m.Switch(cycle):

‎amaranth_soc/wishbone/bus.py‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
from amaranth import *
22
from amaranth.lib import enum, wiring
33
from amaranth.lib.wiring import In, Out, flipped
4-
from amaranth.utils import log2_int
4+
from amaranth.utils import exact_log2
55

66
from ..memory import MemoryMap
77

@@ -273,7 +273,7 @@ def memory_map(self, memory_map):
273273
if memory_map.data_width != self.granularity:
274274
raise ValueError(f"Memory map has data width {memory_map.data_width}, which is "
275275
f"not the same as bus interface granularity {self.granularity}")
276-
granularity_bits = log2_int(self.data_width // self.granularity)
276+
granularity_bits = exact_log2(self.data_width // self.granularity)
277277
effective_addr_width = self.addr_width + granularity_bits
278278
if memory_map.addr_width != max(1, effective_addr_width):
279279
raise ValueError(f"Memory map has address width {memory_map.addr_width}, which is "
@@ -318,7 +318,7 @@ def __init__(self, *, addr_width, data_width, granularity=None, features=frozens
318318
super().__init__({"bus": In(Signature(addr_width=addr_width, data_width=data_width,
319319
granularity=granularity, features=features))})
320320
self.bus.memory_map = MemoryMap(
321-
addr_width=max(1, addr_width + log2_int(data_width // granularity)),
321+
addr_width=max(1, addr_width + exact_log2(data_width // granularity)),
322322
data_width=granularity, alignment=alignment, name=name)
323323
self._subs = dict()
324324

@@ -382,7 +382,7 @@ def elaborate(self, platform):
382382
sub_bus = self._subs[sub_map]
383383

384384
m.d.comb += [
385-
sub_bus.adr.eq(self.bus.adr << log2_int(sub_ratio)),
385+
sub_bus.adr.eq(self.bus.adr << exact_log2(sub_ratio)),
386386
sub_bus.dat_w.eq(self.bus.dat_w),
387387
sub_bus.sel.eq(Cat(sel.replicate(sub_ratio) for sel in self.bus.sel)),
388388
sub_bus.we.eq(self.bus.we),
@@ -395,7 +395,7 @@ def elaborate(self, platform):
395395
if hasattr(sub_bus, "bte"):
396396
m.d.comb += sub_bus.bte.eq(getattr(self.bus, "bte", BurstTypeExt.LINEAR))
397397

398-
granularity_bits = log2_int(self.bus.data_width // self.bus.granularity)
398+
granularity_bits = exact_log2(self.bus.data_width // self.bus.granularity)
399399
with m.Case(sub_pat[:-granularity_bits if granularity_bits > 0 else None]):
400400
m.d.comb += [
401401
sub_bus.cyc.eq(self.bus.cyc),

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