Rename nMigen to Amaranth HDL.

Author: whitequark

CONTRIBUTING.txt

@@ -7,8 +7,8 @@ this purpose.
 
 COPYRIGHTS and LICENSE
 
-nMigen is licensed under the 2-clause BSD license, which is contained in the
-LICENSE.txt file.
+Amaranth HDL is licensed under the 2-clause BSD license, which is contained in
+the LICENSE.txt file.
 
 All authors retain copyright ownership of their contributions.
 

LICENSE.txt

@@ -1,5 +1,4 @@
-Copyright (C) 2019-2020 whitequark
-Copyright (C) 2011-2019 M-Labs Limited
+Copyright (C) 2019-2021 Amaranth HDL contributors
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:

README.md

@@ -1,11 +1,9 @@
-# nMigen boards and connectors
+# Amaranth HDL board definitions
 
-## Ready to use board and connector pinouts, and programming scripts
+TODO
 
-TBD
+## License
 
-### License
-
-nMigen is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use nMigen for closed-source proprietary designs.
+Amaranth is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use Amaranth for closed-source proprietary designs.
 
 See LICENSE file for full copyright and license info.

amaranth_boards/__init__.py

@@ -0,0 +1,11 @@
+try:
+    try:
+        from importlib import metadata as importlib_metadata # py3.8+ stdlib
+    except ImportError:
+        import importlib_metadata # py3.7- shim
+    __version__ = importlib_metadata.version(__package__)
+except ImportError:
+    # No importlib_metadata. This shouldn't normally happen, but some people prefer not installing
+    # packages via pip at all, instead using PYTHONPATH directly or copying the package files into
+    # `lib/pythonX.Y/site-packages`. Although not a recommended way, we still try to support it.
+    __version__ = "unknown" # :nocov:

amaranth_boards/alchitry_au.py

@@ -0,0 +1,76 @@
+import os
+import subprocess
+import shutil
+
+from amaranth.build import *
+from amaranth.vendor.xilinx_7series import *
+from .resources import *
+
+
+__all__ = ["AlchitryAuPlatform"]
+
+
+def find_loader():
+    loader_prgm = os.environ.get("ALCHITRY_LOADER", shutil.which("loader"))
+    if loader_prgm is None:
+        raise EnvironmentError("Could not find Alchrity Loader. Place "
+            "it directly in PATH or specify path explicitly via the "
+            "ALCHITRY_LOADER environment variable")
+    bridge_bin = os.environ.get("ALCHITRY_BRIDGE_BIN", os.path.join(os.path.dirname(loader_prgm), "au_loader.bin"))
+    return (loader_prgm, bridge_bin)
+
+
+class AlchitryAuPlatform(Xilinx7SeriesPlatform):
+    device      = "XC7A35T" # Artix 7 33K LEs
+    package     = "FTG256"
+    speed       = "1"
+    default_clk = "clk100"
+    resources   = [
+        Resource("clk100", 0, Pins("N14", dir="i"),
+                 Clock(10e7), Attrs(IOSTANDARD="LVCMOS33")),
+
+        # On-Board LED Array
+        *LEDResources(
+            pins="K13 K12 L14 L13 M16 M14 M12 N16",
+            attrs=Attrs(IOSTANDARD="LVCMOS33")),
+
+        Resource("usb", 0,
+            Subsignal("usb_tx", Pins("P16", dir="o")),
+            Subsignal("usb_rx", Pins("P15", dir="i")),
+            Attrs(IOSTANDARD="LVCMOS33")
+        ),
+
+        # TODO: This is untested
+        DDR3Resource(0,
+            rst_n="D13", clk_p="G14", clk_n="F14", clk_en="D15", cs_n="D16", we_n="E11", ras_n="D14", cas_n="D14",
+            a="F12 G16 G15 E16 H11 G12 H16 H12 H16 H13 E12 H14 F13 J15",
+            ba="E13 F15 E15",
+            dqs_p="B15 A15", dqs_n="B9 A10",
+            dq="A13 B16 B14 C11 C13 C16 C12 C14 D8 B11 C8 B10 A12 A8 B12 A9",
+            dm="A14 C9", odt="G11",
+            diff_attrs=Attrs(IOSTANDARD="LVDS"),
+            attrs=Attrs(IOSTANDARD="LVCMOS15")),
+    ]
+
+    connectors  = [
+        Connector("bank", 0, "T8  T7  T5  R5  R8  P8  L2  L3  J1  K1  H1  H2  G1  G2  K5  E6 "
+                             "T10 T9  R6  R7  P9  N9  K2  K3  J4  J5  H3  J3  H4  H5  N6  M6 "),
+        Connector("bank", 1, "D1  E2  A2  B2  E1  F2  F3  F4  A3  B4  A4  A5  B5  B6  A7  B7 "
+                             "B1  C1  C2  C3  D3  E3  C4  D4  G4  G5  E5  F5  D5  D6  C6  C7 "),
+        Connector("bank", 2, "T13 R13 T12 R12 R11 R10 N2  N3  P3  P4  M4  L4  N4  M5  L5  P5 "
+                             "P11 P10 N12 N11 P13 N13 M1  M2  P1  N1  R1  R2  T2  R3  T3  T4 "),
+        Connector("bank", 3, "L14 L13 M12 N16 R16 R15 P14 M15 P16 P15  -   -   -   -   -   - "
+                             "K13 K12 M16 M14 T16 T14 N14   -   -   -  -   -   -   -   -   - ")
+    ]
+
+    def toolchain_program(self, products, name):
+        (loader, bridge_bin) = find_loader()
+        with products.extract("{}.bin".format(name)) as bitstream_filename:
+            subprocess.check_call([loader, "-e", "-f", bitstream_filename,
+                "-p", bridge_bin
+            ])
+
+
+if __name__ == "__main__":
+    from .test.blinky import Blinky
+    AlchitryAuPlatform().build(Blinky(), do_program=True)

amaranth_boards/arrow_deca.py

@@ -0,0 +1,88 @@
+import os
+import subprocess
+
+from amaranth.build import *
+from amaranth.vendor.intel import *
+from .resources import *
+
+
+__all__ = ["ArrowDECAPlatform"]
+
+
+class ArrowDECAPlatform(IntelPlatform):
+    device      = "10M50DA" # MAX 10
+    package     = "F484"
+    speed       = "C6"
+    suffix      = "GES"
+    default_clk = "clk50"
+    resources   = [
+        Resource("clk50", 0, Pins("M8", dir="i"),
+            Clock(50e6), Attrs(io_standard="2.5 V")),
+        Resource("clk50", 1, Pins("P11", dir="i"),
+            Clock(50e6), Attrs(io_standard="3.3 V")),
+        Resource("clk50", 2, Pins("N15", dir="i"),
+            Clock(50e6), Attrs(io_standard="1.5 V")),
+        Resource("clk10", 0, Pins("M9", dir="i"),
+            Clock(10e6), Attrs(io_standard="2.5 V")),
+
+        *LEDResources(
+            pins="C7 C8 A6 B7 C4 A5 B4 C5",
+            invert=True,
+            attrs=Attrs(io_standard="1.2 V")),
+        *ButtonResources(
+            pins="H21 H22",
+            invert=True,
+            attrs=Attrs(io_standard="1.5 V")),
+        *SwitchResources(
+            pins="J21 J22",
+            attrs=Attrs(io_standard="1.5 V")),
+    ]
+    connectors  = [
+        Connector("gpio", 0,
+            "W18  Y18  Y19  AA17 AA20 AA19 AB21 AB20 AB19 Y16  V16  "
+            "AB18 V15  W17  AB17 AA16 AB16 W16  AB15 W15  Y14  AA15 "
+            "AB14 AA14 AB13 AA13 AB12 AA12 AB11 AA11 AB10 Y13  Y11  "
+            "W13  W12  W11  V12  V11  V13  V14  Y17  W14  U15  R13"),
+        Connector("gpio", 1,
+            "Y5   Y6   W6   W7   W8   V8   AB8   V7  R11  AB7  AB6  "
+            "AA7  AA6  Y7   V10  U7   W9   W5   R9   W4    P9  V17  "
+            "W3"),
+    ]
+
+    def toolchain_program(self, products, name):
+        quartus_pgm = os.environ.get("QUARTUS_PGM", "quartus_pgm")
+        with products.extract("{}.sof".format(name)) as bitstream_filename:
+            subprocess.check_call([quartus_pgm, "--haltcc", "--mode", "JTAG",
+                                   "--operation", "P;" + bitstream_filename])
+
+    @property
+    def file_templates(self):
+        # Configure the voltages of the I/O banks by appending the global
+        # assignments to the template. However, we create our own copy of the
+        # file templates before modifying them to avoid modifying the original.
+        return {
+            **super().file_templates,
+            "{{name}}.qsf":
+                super().file_templates.get("{{name}}.qsf") +
+                r"""
+                set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 1A
+                set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 1B
+                set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 2
+                set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3
+                set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 4
+                set_global_assignment -name IOBANK_VCCIO 1.5V -section_id 5
+                set_global_assignment -name IOBANK_VCCIO 1.5V -section_id 6
+                set_global_assignment -name IOBANK_VCCIO 1.8V -section_id 7
+                set_global_assignment -name IOBANK_VCCIO 1.2V -section_id 8
+
+                set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+                set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
+                set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+                set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+                """
+        }
+
+
+if __name__ == "__main__":
+    from .test.blinky import Blinky
+    ArrowDECAPlatform().build(Blinky(), do_program=True)