[breaking-change] Add _n suffix to argument names of pins with fixed inverters.

Note: this change does NOT affect pin functionality or naming, and
does not require modifying your design. It does however affect some
board files, where keywords corresponding to active low pins will have
to be adjusted:
    SPIResource(0, cs="C1", ...) → SPIResource(0, cs_n="C1", ...)

The new naming scheme will make it easier to write and audit board
files by clearly marking inverted pins in resource factories, similarly to
how `PinsN` indicates the same in bare resources.

Fixes #129.

Author: GuzTech

nmigen_boards/arty_a7.py

@@ -36,7 +36,7 @@ class ArtyA7Platform(Xilinx7SeriesPlatform):
         ),
 
         SPIResource(0,
-            cs="C1", clk="F1", copi="H1", cipo="G1",
+            cs_n="C1", clk="F1", copi="H1", cipo="G1",
             attrs=Attrs(IOSTANDARD="LVCMOS33")
         ),
 
@@ -49,7 +49,7 @@ class ArtyA7Platform(Xilinx7SeriesPlatform):
         ),
 
         *SPIFlashResources(0,
-            cs="L13", clk="L16", copi="K17", cipo="K18", wp="L14", hold="M14",
+            cs_n="L13", clk="L16", copi="K17", cipo="K18", wp_n="L14", hold_n="M14",
             attrs=Attrs(IOSTANDARD="LVCMOS33")
         ),
 

nmigen_boards/arty_s7.py

@@ -34,7 +34,7 @@ class _ArtyS7Platform(Xilinx7SeriesPlatform):
         ),
 
         SPIResource(0,
-            cs="H16", clk="G16", copi="H17", cipo="K14",
+            cs_n="H16", clk="G16", copi="H17", cipo="K14",
             attrs=Attrs(IOSTANDARD="LVCMOS33")
         ),
 
@@ -44,7 +44,7 @@ class _ArtyS7Platform(Xilinx7SeriesPlatform):
         ),
 
         *SPIFlashResources(0,
-            cs="M13", clk="D11", copi="K17", cipo="K18", wp="L14", hold="M15",
+            cs_n="M13", clk="D11", copi="K17", cipo="K18", wp_n="L14", hold_n="M15",
             attrs=Attrs(IOSTANDARD="LVCMOS33")
         ),
 

nmigen_boards/atlys.py

@@ -71,7 +71,7 @@ def bank2_iostandard(self):
         ),
 
         *SPIFlashResources(0,
-            cs="AE14", clk="AH18", copi="AF14", cipo="AF20", wp="AG21", hold="AG17",
+            cs_n="AE14", clk="AH18", copi="AF14", cipo="AF20", wp_n="AG21", hold_n="AG17",
             attrs=Attrs(IOSTANDARD="LVCMOS25", SLEW="FAST"),
         ),
 

nmigen_boards/blackice.py

@@ -34,7 +34,7 @@ class BlackIcePlatform(LatticeICE40Platform):
         ),
 
         SRAMResource(0,
-            cs="136", oe="45", we="120",
+            cs_n="136", oe_n="45", we_n="120",
             a="137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
             d="135 134 130 128 125 124 122 121 61 60 56 55 52 49 48 47",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS"),

nmigen_boards/blackice_ii.py

@@ -35,10 +35,10 @@ class BlackIceIIPlatform(LatticeICE40Platform):
         ),
 
         SRAMResource(0,
-            cs="136", oe="29", we="120",
+            cs_n="136", oe_n="29", we_n="120",
             a="137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
             d="136 135 134 130 125 124 122 121 62 61 60 56 55 48 47 45",
-            dm="24 28",
+            dm_n="24 28",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS"),
         ),
     ]

nmigen_boards/de0.py

@@ -78,18 +78,18 @@ class DE0Platform(IntelPlatform):
         ),
 
         *SDCardResources(0,
-            clk="Y21", cmd="Y22", dat0="AA22", dat3="W21", wp="W20",
+            clk="Y21", cmd="Y22", dat0="AA22", dat3="W21", wp_n="W20",
             attrs=Attrs(io_standard="3.3-V LVTTL")),
 
         SDRAMResource(0,
-            clk="E5", cke="E6", cs="G7", we="D6", ras="F7", cas="G8",
+            clk="E5", cke="E6", cs_n="G7", we_n="D6", ras_n="F7", cas_n="G8",
             ba="B5 A4", a="C4 A3 B3 C3 A5 C6 B6 A6 C7 B7 B4 A7 C8",
             dq="D10 G10 H10 E9 F9 G9 H9 F8 A8 B9 A9 C10 B10 A10 E10 F10", dqm="E7 B8",
             attrs=Attrs(io_standard="3.3-V LVTTL")),
 
         *NORFlashResources(0,
-            rst="R1", byte="AA1",
-            cs="N8", oe="R6", we="P4", wp="T3", by="M7",
+            rst="R1", byte_n="AA1",
+            cs_n="N8", oe_n="R6", we_n="P4", wp_n="T3", by="M7",
             a="P7 P5 P6 N7 N5 N6 M8 M4 P2 N2 N1 M3 M2 M1 L7 L6 AA2 M5 M6 P1 P3 R2",
             dq="R7 P8 R8 U1 V2 V3 W1 Y1 T5 T7 T4 U2 V1 V4 W2 Y2",
             attrs=Attrs(io_standard="3.3-V LVTTL")),

nmigen_boards/de0_cv.py

@@ -77,7 +77,7 @@ class DE0CVPlatform(IntelPlatform):
             attrs=Attrs(io_standard="3.3-V LVTTL")),
 
         SDRAMResource(0,
-            clk="AB11", cke="R6", cs="U6", we="AB5", ras="AB6", cas="V6",
+            clk="AB11", cke="R6", cs_n="U6", we_n="AB5", ras_n="AB6", cas_n="V6",
             ba="T7 AB7", a="W8 T8 U11 Y10 N6 AB10 P12 P7 P8 R5 U8 P6 R7",
             dq="Y9 T10 R9 Y11 R10 R11 R12 AA12 AA9 AB8 AA8 AA7 V10 V9 U10 T9", dqm="U12 N8",
             attrs=Attrs(io_standard="3.3-V LVCMOS")),

nmigen_boards/de10_lite.py

@@ -56,7 +56,7 @@ class DE10LitePlatform(IntelPlatform):
             attrs=Attrs(io_standard="3.3-V LVTTL")),
 
         SDRAMResource(0,
-            clk="L14", cs="U20", we="V20", ras="U22", cas="U21",
+            clk="L14", cs_n="U20", we_n="V20", ras_n="U22", cas_n="U21",
             ba="T21 T22", a="U17 W19 V18 U18 U19 T18 T19 R18 P18 P19 T20 P20 R20",
             dq="Y21 Y20 AA22 AA21 Y22 W22 W20 V21 P21 J22 H21 H22 G22 G20 G19 F22",
             dqm="V22 J21", attrs=Attrs(io_standard="3.3-V LVCMOS")),

nmigen_boards/de10_nano.py

@@ -40,7 +40,7 @@ class DE10NanoPlatform(IntelPlatform):
 
         # LTC2308 analogue-to-digital converter
         SPIResource(0,
-            cs="U9", clk="V10", copi="AC4", cipo="AD4",
+            cs_n="U9", clk="V10", copi="AC4", cipo="AD4",
             attrs=Attrs(io_standard="3.3-V LVTTL")),
 
         # ADV7513 HDMI transmitter

nmigen_boards/ecp5_5g_evn.py

@@ -70,7 +70,7 @@ def bank6_iostandard(self):
         ),
 
         *SPIFlashResources(0,
-            cs="R2", clk="U3", cipo="V2", copi="W2", wp="Y2", hold="W1",
+            cs_n="R2", clk="U3", cipo="V2", copi="W2", wp_n="Y2", hold_n="W1",
             attrs=Attrs(IO_TYPE="LVCMOS33")
         ),