impl (de)serialize for Zeroable and update CI

Author: alecmocatta

azure-pipelines.yml

@@ -14,19 +14,19 @@ jobs:
     endpoint: alecmocatta
     default:
       rust_toolchain: nightly
-      rust_lint_toolchain: nightly-2019-07-19
+      rust_lint_toolchain: nightly-2020-06-09
       rust_flags: ''
       rust_features: ''
       rust_target_check: ''
       rust_target_build: ''
       rust_target_run: ''
     matrix:
       windows:
-        imageName: 'vs2017-win2016'
+        imageName: 'windows-latest'
         rust_target_run: 'x86_64-pc-windows-msvc i686-pc-windows-msvc' # currently broken building crate-type=lib: x86_64-pc-windows-gnu i686-pc-windows-gnu
       mac:
-        imageName: 'macos-10.13'
+        imageName: 'macos-latest'
         rust_target_run: 'x86_64-apple-darwin i686-apple-darwin'
       linux:
-        imageName: 'ubuntu-16.04'
+        imageName: 'ubuntu-latest'
         rust_target_run: 'x86_64-unknown-linux-gnu i686-unknown-linux-gnu x86_64-unknown-linux-musl i686-unknown-linux-musl'

src/distinct.rs

@@ -54,7 +54,7 @@ use std::{
 use twox_hash::XxHash;
 
 mod consts;
-use self::consts::*;
+use self::consts::{BIAS_DATA, RAW_ESTIMATE_DATA, TRESHOLD_DATA};
 
 /// Like [`HyperLogLog`] but implements `Ord` and `Eq` by using the estimate of the cardinality.
 #[derive(Serialize, Deserialize)]
@@ -429,7 +429,7 @@ impl<V: ?Sized> IntersectPlusUnionIsPlus for HyperLogLog<V> {
 
 #[cfg(target_feature = "avx512bw")] // TODO
 mod simd_types {
-	use super::*;
+	use super::packed_simd;
 	pub type u8s = packed_simd::u8x64;
 	pub type u8s_sad_out = packed_simd::u64x8;
 	pub type f32s = packed_simd::f32x16;
@@ -439,7 +439,7 @@ mod simd_types {
 #[cfg(target_feature = "avx2")]
 mod simd_types {
 	#![allow(non_camel_case_types)]
-	use super::*;
+	use super::packed_simd;
 	pub type u8s = packed_simd::u8x32;
 	pub type u8s_sad_out = packed_simd::u64x4;
 	pub type f32s = packed_simd::f32x8;
@@ -449,7 +449,7 @@ mod simd_types {
 #[cfg(all(not(target_feature = "avx2"), target_feature = "sse2"))]
 mod simd_types {
 	#![allow(non_camel_case_types)]
-	use super::*;
+	use super::packed_simd;
 	pub type u8s = packed_simd::u8x16;
 	pub type u8s_sad_out = packed_simd::u64x2;
 	pub type f32s = packed_simd::f32x4;
@@ -459,14 +459,14 @@ mod simd_types {
 #[cfg(all(not(target_feature = "avx2"), not(target_feature = "sse2")))]
 mod simd_types {
 	#![allow(non_camel_case_types)]
-	use super::*;
+	use super::packed_simd;
 	pub type u8s = packed_simd::u8x8;
 	pub type u8s_sad_out = u64;
 	pub type f32s = packed_simd::f32x2;
 	pub type u32s = packed_simd::u32x2;
 	pub type u8sq = packed_simd::u8x2;
 }
-use self::simd_types::*;
+use self::simd_types::{f32s, u32s, u8s, u8s_sad_out, u8sq};
 
 struct Sad<X>(PhantomData<fn(X)>);
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]

src/lib.rs

@@ -44,7 +44,10 @@
 	clippy::op_ref,
 	clippy::needless_pass_by_value,
 	clippy::suspicious_op_assign_impl,
-	clippy::float_cmp
+	clippy::float_cmp,
+	clippy::unsafe_derive_deserialize,
+	clippy::must_use_candidate,
+	clippy::unused_self
 )]
 
 mod count_min;

src/sample.rs

@@ -220,7 +220,6 @@ impl<T> ops::AddAssign for SampleUnstable<T> {
 #[cfg(test)]
 mod test {
 	use super::*;
-	use rand;
 	use std::collections::HashMap;
 
 	#[test]

src/top.rs

@@ -153,13 +153,14 @@ impl<'a, A: Hash + Eq + Clone + Debug, C: Ord + Debug + 'a> Debug for TopIter<'a
 }
 
 /// For the result of a `std::iter::sum()` when an additive identity (i.e. zero) can't be constructed (in the case where we're summing an empty iterator).
-#[derive(Copy, Clone, Debug)]
+#[derive(Copy, Clone, Serialize, Deserialize, Debug)]
 pub enum Zeroable<T> {
 	/// Zero
 	Zero,
 	/// Nonzero
 	Nonzero(T),
 }
+#[allow(clippy::missing_errors_doc)]
 impl<T> Zeroable<T> {
 	/// Transform to a `Result<T, E>`.
 	pub fn ok_or<E>(self, err: E) -> Result<T, E> {