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4 changes: 2 additions & 2 deletions shiva.h
Original file line number Diff line number Diff line change
Expand Up @@ -232,7 +232,7 @@ struct shiva_branch_site {
#define SHIVA_XREF_F_DEREF_SYMINFO (1UL << 3)
#define SHIVA_XREF_F_TO_SECTION (1UL << 4) /* xref to a section (i.e. .rodata) with no syminfo */

struct shiva_xref_site {
typedef struct shiva_xref_site {
int type;
uint64_t flags;
uint64_t *got; // indirect xrefs use a .got to hold a symbol value.
Expand Down Expand Up @@ -370,7 +370,7 @@ typedef struct shiva_transform {
* after ld-linux.so is completely done and passes
* control back to Shiva AT_ENTRY, if needed.
*/
struct shiva_module_delayed_reloc {
typedef struct shiva_module_delayed_reloc {
uint8_t *rel_unit;
uint64_t rel_addr;
uint64_t symval; /* The symbols value */
Expand Down
26 changes: 9 additions & 17 deletions shiva_analyze.c
Original file line number Diff line number Diff line change
Expand Up @@ -224,27 +224,19 @@ shiva_analyze_find_calls(struct shiva_ctx *ctx)
#endif
shiva_debug("0x%"PRIx64":\t%s\t\t%s\n", ctx->disas.insn->address,
ctx->disas.insn->mnemonic, ctx->disas.insn->op_str);
if (strcmp(ctx->disas.insn->mnemonic, "b") == 0) {
if (shiva_analyze_build_aarch64_jmp(ctx, section.address + c)
== false) {
fprintf(stderr, "shiva_analyze_build_aarch64_jmp(%p, %#lx) failed\n",
ctx, section.address + c);
return false;
}
}
if (strncmp(ctx->disas.insn->mnemonic, "b.", 2) == 0) {
if (ctx->disas.insn->id == ARM64_INS_B) {
/*
* Branch instructions:
* b.eq, b.ne, b.gt, b.ge, b.lt, b.le, b.ls, b.hi,
* b.cc, b.cs, b.cond
* b.cc, b.cs, b.cond, b
*/
if (shiva_analyze_build_aarch64_jmp(ctx, section.address + c)
== false) {
fprintf(stderr, "shiva_analyze_build_aarch64_jmp(%p, %#lx) failed\n",
ctx, section.address + c);
return false;
}
} else if (strncmp(ctx->disas.insn->mnemonic, "cb", 2) == 0) {
} else if (ctx->disas.insn->id == ARM64_INS_CBNZ || ctx->disas.insn->id == ARM64_INS_CBZ) {
/*
* Compare and branch
* cbnz, cbz
Expand All @@ -256,7 +248,7 @@ shiva_analyze_find_calls(struct shiva_ctx *ctx)
return false;
}

} else if (strncmp(ctx->disas.insn->mnemonic, "tb", 2) == 0) {
} else if (ctx->disas.insn->id == ARM64_INS_TBNZ || ctx->disas.insn->id == ARM64_INS_TBZ) {
/*
* Test bit and branch
* tbz, tbnz
Expand All @@ -268,7 +260,7 @@ shiva_analyze_find_calls(struct shiva_ctx *ctx)
return false;
}

} else if (strcmp(ctx->disas.insn->mnemonic, "bl") == 0) {
} else if (ctx->disas.insn->id == ARM64_INS_BL) {
struct shiva_branch_site *tmp;
uint64_t addr;
struct elf_symbol tmp_sym;
Expand Down Expand Up @@ -338,7 +330,7 @@ shiva_analyze_find_calls(struct shiva_ctx *ctx)
shiva_debug("Inserting branch for symbol %s callsite: %#lx\n", tmp->symbol.name, tmp->branch_site);
TAILQ_INSERT_TAIL(&ctx->tailq.branch_tqlist, tmp, _linkage);
shiva_debug("Done inserting it\n");
} else if (strcmp(ctx->disas.insn->mnemonic, "adrp") == 0) {
} else if (ctx->disas.insn->id == ARM64_INS_ADRP) {
uint64_t adrp_imm, adrp_site;
uint32_t adrp_o_bytes = *(uint32_t *)ctx->disas.insn->bytes;
uint32_t next_o_bytes;
Expand Down Expand Up @@ -383,11 +375,11 @@ shiva_analyze_find_calls(struct shiva_ctx *ctx)
/*
* Is the next instruction and ldr?
*/
if (strcmp(ctx->disas.insn->mnemonic, "ldr") == 0) {
if (ctx->disas.insn->id == ARM64_INS_LDR) {
xref_type = SHIVA_XREF_TYPE_ADRP_LDR;
} else if (strcmp(ctx->disas.insn->mnemonic, "str") == 0) {
} else if (ctx->disas.insn->id == ARM64_INS_STR) {
xref_type = SHIVA_XREF_TYPE_ADRP_STR;
} else if (strcmp(ctx->disas.insn->mnemonic, "add") == 0) {
} else if (ctx->disas.insn->id == ARM64_INS_ADD) {
xref_type = SHIVA_XREF_TYPE_ADRP_ADD;
} else {
xref_type = SHIVA_XREF_TYPE_UNKNOWN;
Expand Down