ch32v: Add time and clocks config (#742)

Grazfather · Grazfather · commit 97131a0fa707 · 2025-11-30T20:08:06.000-05:00
diff --git a/examples/wch/ch32v/src/blinky_systick.zig b/examples/wch/ch32v/src/blinky_systick.zig
@@ -10,6 +10,7 @@ else
     hal.gpio.Pin.init(0, 3); // PA3
 
 pub const microzig_options: microzig.Options = .{
+    .overwrite_hal_interrupts = true,
     .interrupts = .{
         .SysTick = sys_tick_handler,
     },
diff --git a/examples/wch/ch32v/src/board_blinky.zig b/examples/wch/ch32v/src/board_blinky.zig
@@ -1,4 +1,5 @@
 const microzig = @import("microzig");
+const hal = microzig.hal;
 const board = microzig.board;
 
 // Can define in the board file.
@@ -12,6 +13,9 @@ const board = microzig.board;
 // };
 
 pub fn main() !void {
+    // Board brings up clocks and time
+    board.init();
+
     const pins = board.pin_config.apply();
 
     while (true) {
@@ -22,18 +26,6 @@ pub fn main() !void {
         // }
         pins.led.toggle();
 
-        busy_delay(1000);
-    }
-}
-
-inline fn busy_delay(comptime ms: u32) void {
-    const cpu_frequency = board.cpu_frequency;
-    const cycles_per_ms = cpu_frequency / 1_000;
-    const loop_cycles = 3;
-    const limit = cycles_per_ms * ms / loop_cycles;
-
-    var i: u32 = 0;
-    while (i < limit) : (i += 1) {
-        asm volatile ("" ::: .{ .memory = true });
+        hal.time.sleep_ms(1000);
     }
 }
diff --git a/port/wch/ch32v/build.zig b/port/wch/ch32v/build.zig
@@ -2,6 +2,9 @@ const std = @import("std");
 const microzig = @import("microzig/build-internals");
 const CpuName = @import("src/cpus/main.zig").CpuName;
 
+// Technical reference manuals:
+// 003: https://ch32-riscv-ug.github.io/CH32V003/datasheet_en/CH32V003RM.PDF
+// 20x, 30x, 31x: https://static.chipdip.ru/lib/820/DOC059820997.pdf
 const Self = @This();
 
 const KiB = 1024;
@@ -67,7 +70,10 @@ const BaseChip = struct {
 };
 
 // Generated with:
-// curl 'https://www.wch-ic.com/api/product_tables/47?page=1&limit=100' | jq -r '.data[] | select(.["Part NO."] | startswith("CH32V")) | [ "    ", (.["Part NO."] | ascii_downcase), ": *const microzig.Target, // ", .Flash, " / ", .SRAM, " / ", .Freq ] | join("")' | awk 'match($0, /    ch32v/) { $0 = substr($0, 1, RSTART+11) "x" substr($0, RSTART+13, 1) substr($0, RSTART+16) }; {print}' | sort -n | uniq
+// curl 'https://www.wch-ic.com/api/product_tables/47?page=1&limit=100' |
+// jq -r '.data[] | select(.["Part NO."] | startswith("CH32V")) | [ "    ", (.["Part NO."] | ascii_downcase), ": *const microzig.Target, // ", .Flash, " / ", .SRAM, " / ", .Freq ] | join("")' |
+// awk 'match($0, /    ch32v/) { $0 = substr($0, 1, RSTART+11) "x" substr($0, RSTART+13, 1) substr($0, RSTART+16) }; {print}' |
+// sort -n | uniq
 chips: struct {
     ch32v003x4: *const microzig.Target, // 16K / 2K / 48MHz
     ch32v103x6: *const microzig.Target, // 32K / 10K / 80MHz
@@ -91,6 +97,7 @@ boards: struct {
     },
     ch32v203: struct {
         suzuduino_uno_v1b: *const microzig.Target,
+        lana_tny: *const microzig.Target,
     },
     ch32v305: struct {
         nano_ch32v305: *const microzig.Target,
@@ -191,6 +198,14 @@ pub fn init(dep: *std.Build.Dependency) Self {
         },
     });
 
+    const board_lana_tny = chip_ch32v203x6.derive(.{
+        .board = .{
+            .name = "LANA TNY",
+            .url = "https://phyx.be/LANA_TNY/",
+            .root_source_file = b.path("src/boards/LANA_TNY.zig"),
+        },
+    });
+
     return .{
         .chips = .{
             .ch32v003x4 = chip_ch32v003x4,
@@ -215,6 +230,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
             },
             .ch32v203 = .{
                 .suzuduino_uno_v1b = board_suzuduino_uno_v1b,
+                .lana_tny = board_lana_tny,
             },
             .ch32v305 = .{
                 .nano_ch32v305 = board_nano_ch32v305,
diff --git a/port/wch/ch32v/src/boards/CH32V103-R1-1v1.zig b/port/wch/ch32v/src/boards/CH32V103-R1-1v1.zig
@@ -2,5 +2,12 @@
 // CH32V103
 pub const chip = @import("chip");
 pub const microzig = @import("microzig");
+const ch32v = microzig.hal;
 
-pub const cpu_frequency = 8_000_000; // 8 MHz
+pub const cpu_frequency = 48_000_000; // 48 MHz
+
+/// Board-specific init: set 48 MHz clock, enable SysTick time
+pub fn init() void {
+    ch32v.clocks.init_48mhz_hsi();
+    ch32v.time.init();
+}
diff --git a/port/wch/ch32v/src/boards/CH32V307V-R1-1v0.zig b/port/wch/ch32v/src/boards/CH32V307V-R1-1v0.zig
@@ -1,5 +1,13 @@
 // CH32V307V_MINI
 // CH32V307
+pub const microzig = @import("microzig");
 pub const chip = @import("chip");
+const ch32v = microzig.hal;
 
-pub const cpu_frequency = 8_000_000; // 8 MHz
+pub const cpu_frequency = 48_000_000; // 48 MHz
+
+/// Board-specific init: set 48 MHz clock, enable SysTick time
+pub fn init() void {
+    ch32v.clocks.init_48mhz_hsi();
+    ch32v.time.init();
+}
diff --git a/port/wch/ch32v/src/boards/CH32Vx03C-R0-1v0.zig b/port/wch/ch32v/src/boards/CH32Vx03C-R0-1v0.zig
@@ -1,5 +1,13 @@
 // CH32Vx03C_MINI
 // CH32V203
+pub const microzig = @import("microzig");
 pub const chip = @import("chip");
+const ch32v = microzig.hal;
 
-pub const cpu_frequency = 8_000_000; // 8 MHz
+pub const cpu_frequency = 48_000_000; // 48 MHz
+
+/// Board-specific init: set 48 MHz clock, enable SysTick time
+pub fn init() void {
+    ch32v.clocks.init_48mhz_hsi();
+    ch32v.time.init();
+}
diff --git a/port/wch/ch32v/src/boards/LANA_TNY.zig b/port/wch/ch32v/src/boards/LANA_TNY.zig
@@ -0,0 +1,24 @@
+// LANA TNY Board
+// https://learn.adafruit.com/phyx-lana-tny-ch32v203/pinouts
+// CH32V203
+pub const microzig = @import("microzig");
+pub const chip = @import("chip");
+const ch32v = microzig.hal;
+
+pub const cpu_frequency = 48_000_000; // 48 MHz
+
+/// Board-specific init: set 48 MHz clock, enable SysTick time
+pub fn init() void {
+    ch32v.clocks.init_48mhz_hsi();
+    ch32v.time.init();
+}
+
+pub const pin_config = ch32v.pins.GlobalConfiguration{
+    .GPIOD = .{
+        .PIN0 = .{
+            .name = "ws2812",
+            .mode = .{ .output = .general_purpose_push_pull },
+            .speed = .max_50MHz,
+        },
+    },
+};
diff --git a/port/wch/ch32v/src/boards/Suzuduino_Uno_V1b.zig b/port/wch/ch32v/src/boards/Suzuduino_Uno_V1b.zig
@@ -1,11 +1,11 @@
 // Suzuduino Uno V1b
 // https://github.com/verylowfreq/suzuduino-uno-v1
 // CH32V203
-pub const chip = @import("chip");
 pub const microzig = @import("microzig");
+pub const chip = @import("chip");
 const ch32v = microzig.hal;
 
-pub const cpu_frequency = 8_000_000; // 8 MHz
+pub const cpu_frequency = 48_000_000; // 48 MHz
 
 pub const pin_config = ch32v.pins.GlobalConfiguration{
     .GPIOA = .{
@@ -15,3 +15,9 @@ pub const pin_config = ch32v.pins.GlobalConfiguration{
         },
     },
 };
+
+/// Board-specific init: set 48 MHz clock, enable SysTick time
+pub fn init() void {
+    ch32v.clocks.init_48mhz_hsi();
+    ch32v.time.init();
+}
diff --git a/port/wch/ch32v/src/boards/nanoCH32V305.zig b/port/wch/ch32v/src/boards/nanoCH32V305.zig
@@ -5,7 +5,7 @@ pub const chip = @import("chip");
 pub const microzig = @import("microzig");
 const ch32v = microzig.hal;
 
-pub const cpu_frequency = 8_000_000; // 8 MHz
+pub const cpu_frequency = 48_000_000; // 48 MHz
 
 pub const pin_config = ch32v.pins.GlobalConfiguration{
     .GPIOA = .{
@@ -15,3 +15,9 @@ pub const pin_config = ch32v.pins.GlobalConfiguration{
         },
     },
 };
+
+/// Board-specific init: set 48 MHz clock, enable SysTick time
+pub fn init() void {
+    ch32v.clocks.init_48mhz_hsi();
+    ch32v.time.init();
+}
diff --git a/port/wch/ch32v/src/cpus/main.zig b/port/wch/ch32v/src/cpus/main.zig
@@ -38,6 +38,7 @@ pub const InterruptOptions = microzig.utilities.GenerateInterruptOptions(&.{
     .{ .InterruptEnum = enum { Exception }, .HandlerFn = InterruptHandler },
     .{ .InterruptEnum = Interrupt, .HandlerFn = InterruptHandler },
 });
+const VectorTable = [vector_table_size()]InterruptHandler;
 
 pub const interrupt = struct {
     pub inline fn globally_enabled() bool {
@@ -69,7 +70,12 @@ pub const interrupt = struct {
     pub inline fn enable(irq: Interrupt) void {
         comptime {
             const irq_name = @tagName(irq);
-            if (@field(microzig.options.interrupts, irq_name) == null) {
+            const app_has = @field(microzig.options.interrupts, irq_name) != null;
+            const hal_has = if (microzig.config.has_hal and @hasDecl(microzig.hal, "default_interrupts"))
+                @field(microzig.hal.default_interrupts, irq_name) != null
+            else
+                false;
+            if (!app_has and !hal_has) {
                 @compileError(
                     irq_name ++ " interrupt handler should be defined.\n" ++
                         "Add to your main file:\n" ++
@@ -327,14 +333,15 @@ fn vector_table_size() usize {
     return last_interrupt_idx + 1 - vector_table_offset;
 }
 
-pub fn generate_vector_table() [vector_table_size()]InterruptHandler {
+pub fn generate_vector_table() VectorTable {
     @setEvalBranchQuota(100_000);
+    var tmp: VectorTable = @splat(microzig.options.interrupts.Exception orelse unhandled);
 
     const type_info = @typeInfo(Interrupt);
     const interrupts_list = type_info.@"enum".fields;
 
-    var temp: [vector_table_size()]InterruptHandler = @splat(microzig.options.interrupts.Exception orelse unhandled);
-    for (&temp, vector_table_offset..) |_, idx| {
+    // Apply interrupts
+    for (&tmp, vector_table_offset..) |_, idx| {
         // Find name of the interrupt by its number.
         var name: ?[:0]const u8 = null;
         for (interrupts_list) |decl| {
@@ -345,13 +352,33 @@ pub fn generate_vector_table() [vector_table_size()]InterruptHandler {
         }
 
         if (name) |n| {
-            if (@field(microzig.options.interrupts, n)) |h| {
-                temp[idx - vector_table_offset] = h;
-            }
+            const maybe_handler = @field(microzig.options.interrupts, n);
+            const maybe_default = get_hal_default_handler(n);
+
+            tmp[idx - vector_table_offset] = blk: {
+                if (maybe_handler) |handler| {
+                    if (!microzig.options.overwrite_hal_interrupts and maybe_default != null)
+                        @compileError(std.fmt.comptimePrint(
+                            \\Interrupt {s} is used internally by the HAL; overriding it may cause malfunction.
+                            \\If you are sure of what you are doing, set "overwrite_hal_interrupts" to true in: "microzig_options".
+                            \\
+                        , .{n}));
+                    break :blk handler;
+                } else break :blk maybe_default orelse unhandled;
+            };
         }
     }
 
-    return temp;
+    return tmp;
+}
+
+fn get_hal_default_handler(comptime handler_name: []const u8) ?InterruptHandler {
+    if (microzig.config.has_hal) {
+        if (@hasDecl(microzig.hal, "default_interrupts")) {
+            return @field(microzig.hal.default_interrupts, handler_name);
+        }
+    }
+    return null;
 }
 
 const vector_table = generate_vector_table();
@@ -452,4 +479,9 @@ pub const csr = struct {
     pub const cpmpocr = Csr(0xBC3, u32);
     pub const cmcr = Csr(0xBD0, u32);
     pub const cinfor = Csr(0xFC0, u32);
+
+    // Cycle counters
+    pub const cycle = riscv32_common.csr.cycle;
+    pub const cycleh = riscv32_common.csr.cycleh;
+    pub const mcountinhibit = riscv32_common.csr.mcountinhibit;
 };
diff --git a/port/wch/ch32v/src/hals/ch32v003.zig b/port/wch/ch32v/src/hals/ch32v003.zig
@@ -3,6 +3,7 @@ pub const peripherals = microzig.chip.peripherals;
 
 pub const pins = @import("ch32v003/pins.zig");
 pub const gpio = @import("ch32v003/gpio.zig");
+pub const time = @import("time.zig");
 
 // pub fn init() void {}
 
diff --git a/port/wch/ch32v/src/hals/ch32v103.zig b/port/wch/ch32v/src/hals/ch32v103.zig
@@ -1,4 +1,11 @@
+const microzig = @import("microzig");
 pub const pins = @import("pins.zig");
 pub const gpio = @import("gpio.zig");
+pub const clocks = @import("clocks.zig");
+pub const time = @import("time.zig");
 
-// pub fn init() void {}
+/// Initialize HAL subsystems used by default
+/// CH32V103: set clock to 48 MHz via HSI PLL; SysTick driver differs on 103, so time is not enabled here.
+pub fn init() void {
+    clocks.init_48mhz_hsi();
+}
diff --git a/port/wch/ch32v/src/hals/ch32v20x.zig b/port/wch/ch32v/src/hals/ch32v20x.zig
@@ -1,4 +1,21 @@
+const microzig = @import("microzig");
+
 pub const pins = @import("pins.zig");
 pub const gpio = @import("gpio.zig");
+pub const clocks = @import("clocks.zig");
+pub const time = @import("time.zig");
+
+pub const default_interrupts: microzig.cpu.InterruptOptions = .{
+    // Default SysTick handler provided by the HAL
+    .SysTick = time.systick_handler,
+};
+
+pub fn init() void {
+    time.init();
+}
 
-// pub fn init() void {}
+test "hal tests" {
+    _ = clocks;
+    _ = gpio;
+    _ = time;
+}
diff --git a/port/wch/ch32v/src/hals/ch32v30x.zig b/port/wch/ch32v/src/hals/ch32v30x.zig
@@ -1,4 +1,16 @@
+const microzig = @import("microzig");
 pub const pins = @import("pins.zig");
 pub const gpio = @import("gpio.zig");
+pub const clocks = @import("clocks.zig");
+pub const time = @import("time.zig");
 
-// pub fn init() void {}
+/// Default interrupt handlers provided by the HAL
+pub const default_interrupts: microzig.cpu.InterruptOptions = .{
+    .SysTick = time.systick_handler,
+};
+
+/// Initialize HAL subsystems used by default
+pub fn init() void {
+    // Configure SysTick timing driver
+    time.init();
+}
diff --git a/port/wch/ch32v/src/hals/clocks.zig b/port/wch/ch32v/src/hals/clocks.zig
@@ -0,0 +1,31 @@
+const microzig = @import("microzig");
+
+/// Initialize system clock to 48 MHz using HSI
+pub fn init_48mhz_hsi() void {
+    const RCC = microzig.chip.peripherals.RCC;
+    const EXTEND = microzig.chip.peripherals.EXTEND;
+    // Enable PLL HSI prescaler (HSIPRE bit)
+    EXTEND.EXTEND_CTR.modify(.{ .HSIPRE = 1 });
+
+    // Configure clock prescalers
+    RCC.CFGR0.modify(.{
+        .HPRE = 0, // AHB prescaler = 1 (no division)
+        .PPRE2 = 0, // APB2 prescaler = 1 (no division)
+        .PPRE1 = 4, // APB1 prescaler = 2 (divide by 2)
+        .PLLSRC = 0, // PLL source = HSI/2
+        .PLLXTPRE = 0, // HSE divider for PLL = no division
+        .PLLMUL = 4, // PLL multiplier = 6 (value 4 = 6x)
+    });
+
+    // Enable PLL
+    RCC.CTLR.modify(.{ .PLLON = 1 });
+
+    // Wait for PLL to lock
+    while (RCC.CTLR.read().PLLRDY == 0) {}
+
+    // Select PLL as system clock
+    RCC.CFGR0.modify(.{ .SW = 2 }); // SW = 2 means PLL
+
+    // Wait for PLL to be used as system clock (SWS should be 2)
+    while (RCC.CFGR0.read().SWS != 2) {}
+}
diff --git a/port/wch/ch32v/src/hals/gpio.zig b/port/wch/ch32v/src/hals/gpio.zig
@@ -1,5 +1,3 @@
-// const std = @import("std");
-
 const microzig = @import("microzig");
 pub const peripherals = microzig.chip.peripherals;
 
diff --git a/port/wch/ch32v/src/hals/time.zig b/port/wch/ch32v/src/hals/time.zig
