Implement i32x4.dot_i16x8_s (#393)

It multiplies respective lanes from the 2 input operands, then adds
adjacent lanes.

This was merged into the proposal in #127.

Author: ngzhian

interpreter/binary/decode.ml

@@ -370,6 +370,7 @@ let simd_prefix s =
   | 0xb7l -> i32x4_min_u
   | 0xb8l -> i32x4_max_s
   | 0xb9l -> i32x4_max_u
+  | 0xbal -> i32x4_dot_i16x8_s
   | 0xc1l -> i64x2_neg
   | 0xcbl -> i64x2_shl
   | 0xccl -> i64x2_shr_s

interpreter/binary/encode.ml

@@ -466,6 +466,7 @@ let encode m =
       | Binary (V128 V128Op.(I32x4 MinU)) -> simd_op 0xb7l
       | Binary (V128 V128Op.(I32x4 MaxS)) -> simd_op 0xb8l
       | Binary (V128 V128Op.(I32x4 MaxU)) -> simd_op 0xb9l
+      | Binary (V128 V128Op.(I32x4 DotI16x8S)) -> simd_op 0xbal
       | Binary (V128 V128Op.(I32x4 Mul)) -> simd_op 0xb5l
       | Binary (V128 V128Op.(I32x4 Eq)) -> simd_op 0x37l
       | Binary (V128 V128Op.(I32x4 Ne)) -> simd_op 0x38l

interpreter/exec/eval_simd.ml

@@ -118,6 +118,7 @@ module SimdOp (SXX : Simd.S) (Value : ValueType with type t = SXX.t) = struct
       | I32x4 GtU -> SXX.I32x4.gt_u
       | I32x4 GeS -> SXX.I32x4.ge_s
       | I32x4 GeU -> SXX.I32x4.ge_u
+      | I32x4 DotI16x8S -> SXX.I32x4_convert.dot_i16x8_s
       | I64x2 Add -> SXX.I64x2.add
       | I64x2 Sub -> SXX.I64x2.sub
       | I64x2 Mul -> SXX.I64x2.mul

interpreter/exec/simd.ml

@@ -185,6 +185,7 @@ sig
     val widen_high_s : t -> t
     val widen_low_u : t -> t
     val widen_high_u : t -> t
+    val dot_i16x8_s : t -> t -> t
   end
   module I64x2_convert : sig
     val widen_low_s : t -> t
@@ -429,6 +430,17 @@ struct
     let widen_high_s = widen Lib.List.drop 0xffffffffl
     let widen_low_u = widen Lib.List.take 0xffffl
     let widen_high_u = widen Lib.List.drop 0xffffl
+
+    let dot_i16x8_s x y =
+      let xs = Rep.to_i16x8 x in
+      let ys = Rep.to_i16x8 y in
+      let rec dot xs ys =
+        match xs, ys with
+        | x1::x2::xss, y1::y2::yss ->
+          Int32.(add (mul x1 y1) (mul x2 y2)) :: dot xss yss
+        | [], [] -> []
+        | _, _ -> assert false
+      in Rep.of_i32x4 (dot xs ys)
   end
 
   module I64x2_convert = struct

interpreter/syntax/ast.ml

@@ -54,6 +54,7 @@ struct
               | Eq | Ne | LtS | LtU | LeS | LeU | GtS | GtU | GeS | GeU
               | Swizzle | Shuffle of int list | NarrowS | NarrowU
               | AddSatS | AddSatU | SubSatS | SubSatU
+              | DotI16x8S
   type funop = Abs | Neg | Sqrt
              | Ceil | Floor | Trunc | Nearest
              | ConvertI32x4S | ConvertI32x4U

interpreter/syntax/operators.ml

@@ -367,6 +367,7 @@ let i32x4_max_u = Binary (V128 V128Op.(I32x4 MaxU))
 let i32x4_mul = Binary (V128 V128Op.(I32x4 Mul))
 let i32x4_trunc_sat_f32x4_s = Unary (V128 V128Op.(I32x4 TruncSatF32x4S))
 let i32x4_trunc_sat_f32x4_u = Unary (V128 V128Op.(I32x4 TruncSatF32x4U))
+let i32x4_dot_i16x8_s = Binary (V128 V128Op.(I32x4 DotI16x8S))
 
 let i64x2_splat = Convert (V128 V128Op.(I64x2 Splat))
 let i64x2_extract_lane imm = SimdExtract (V128Op.I64x2 (ZX, imm))

interpreter/text/arrange.ml

@@ -305,6 +305,7 @@ struct
     | I32x4 MinU -> "i32x4.min_u"
     | I32x4 MaxS -> "i32x4.max_s"
     | I32x4 MaxU -> "i32x4.max_u"
+    | I32x4 DotI16x8S -> "i32x4.dot_i16x8_s"
     | I64x2 Add -> "i64x2.add"
     | I64x2 Sub -> "i64x2.sub"
     | I64x2 Mul -> "i64x2.mul"

interpreter/text/lexer.mll

@@ -569,6 +569,9 @@ rule token = parse
   | "i16x8.sub_sat_"(sign as s)
   { BINARY (ext s i16x8_sub_sat_s i16x8_sub_sat_u) }
 
+  | "i32x4.dot_i16x8_s"
+  { BINARY i32x4_dot_i16x8_s }
+
   | (simd_shape as s) { SIMD_SHAPE (simd_shape s) }
 
   | name as s { VAR s }

test/core/simd/meta/README.md

@@ -26,6 +26,7 @@ Currently it only support following simd test files generation.
 - 'simd_f64x2_rounding'
 - 'simd_f32x4_pmin_pmax'
 - 'simd_f64x2_pmin_pmax'
+- 'simd_i32x4_dot_i16x8'
 
 
 Usage:

test/core/simd/meta/gen_tests.py

@@ -30,6 +30,7 @@
     'simd_f64x2_rounding',
     'simd_f32x4_pmin_pmax',
     'simd_f64x2_pmin_pmax',
+    'simd_i32x4_dot_i16x8',
 )