55"""
66
77from simd import SIMD
8- from test_assert import AssertReturn , AssertInvalid
8+ from test_assert import AssertReturn , AssertInvalid , AssertMalformed
99from simd_lane_value import LaneValue
1010from simd_integer_op import IntegerSimpleOp as IntOp
1111
@@ -17,7 +17,7 @@ class SimdLaneWiseInteger:
1717
1818 BINARY_OPS = ('min_s' , 'min_u' , 'max_s' , 'max_u' ,)
1919
20- class_summary = """;; Tests for {lane_type} [min_s, min_u, max_s, max_u] operations."""
20+ class_summary = """;; Tests for {lane_type} [min_s, min_u, max_s, max_u, avgr_u ] operations."""
2121
2222 def __init__ (self ):
2323
@@ -246,21 +246,15 @@ def gen(case_data):
246246 @property
247247 def gen_test_case_unknown_operators (self ):
248248 """generate unknown operators test cases"""
249-
250- if self .LANE_TYPE != 'i32x4' :
251- return ''
252-
253- cases = '\n \n ;; Unknown operators'
254- lane_types = ('f32x4' , 'i64x2' ,)
255- assert_template = '(assert_malformed (module quote "(memory 1) (func (result v128) ({lane_type}.{op} {param_1} {param_2}))") "unknown operator")'
256- for lane_type in lane_types :
257- for op in self .BINARY_OPS :
258- cases += '\n ' + assert_template .format (lane_type = lane_type ,
259- op = op ,
260- param_1 = SIMD .v128_const ('0' , self .LANE_TYPE ),
261- param_2 = SIMD .v128_const ('1' , self .LANE_TYPE ))
262-
263- return cases
249+ cases = ['\n \n ;; Unknown operators' ]
250+
251+ for op in self .UNKNOWN_OPS :
252+ cases .append (AssertMalformed .get_unknown_op_test (
253+ op , 'v128' ,
254+ SIMD .v128_const ('0' , self .LANE_TYPE ),
255+ SIMD .v128_const ('1' , self .LANE_TYPE )
256+ ))
257+ return '\n ' .join (cases )
264258
265259 @property
266260 def gen_test_case_type_check (self ):
@@ -373,15 +367,28 @@ def gen_test_cases(self):
373367
374368class Simdi32x4Case (SimdLaneWiseInteger ):
375369 LANE_TYPE = 'i32x4'
370+ class_summary = """;; Tests for {lane_type} [min_s, min_u, max_s, max_u] operations."""
371+
372+ UNKNOWN_OPS = ('f32x4.min_s' , 'f32x4.min_u' , 'f32x4.max_s' , 'f32x4.max_u' ,
373+ 'i64x2.min_s' , 'i64x2.min_u' , 'i64x2.max_s' , 'i64x2.max_u' ,
374+ 'f64x2.min_s' , 'f64x2.min_u' , 'f64x2.max_s' , 'f64x2.max_u' )
376375
377376
378377class Simdi16x8Case (SimdLaneWiseInteger ):
379378 LANE_TYPE = 'i16x8'
380379
380+ BINARY_OPS = ('min_s' , 'min_u' , 'max_s' , 'max_u' , 'avgr_u' )
381+ UNKNOWN_OPS = ('i16x8.avgr' , 'i16x8.avgr_s' )
382+
381383
382384class Simdi8x16Case (SimdLaneWiseInteger ):
383385 LANE_TYPE = 'i8x16'
384386
387+ BINARY_OPS = ('min_s' , 'min_u' , 'max_s' , 'max_u' , 'avgr_u' )
388+ UNKNOWN_OPS = ('i32x4.avgr_u' , 'f32x4.avgr_u' ,
389+ 'i64x2.avgr_u' , 'f64x2.avgr_u' ,
390+ 'i8x16.avgr' , 'i8x16.avgr_s' )
391+
385392
386393def gen_test_cases ():
387394 simd_i32x4_case = Simdi32x4Case ()
@@ -395,4 +402,4 @@ def gen_test_cases():
395402
396403
397404if __name__ == '__main__' :
398- gen_test_cases ()
405+ gen_test_cases ()
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