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ngzhianngzhian
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Rename SIMD load splats and load extends. (#322)
Following suggestions in #297, renaming load splats and load extends to something more consistent. Fixed #297.
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-496
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11 files changed

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‎interpreter/binary/decode.ml‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -222,16 +222,16 @@ let simd_prefix s =
222222
let pos = pos s in
223223
match vu32 s with
224224
| 0x00l -> let a, o = memop s in v128_load a o
225-
| 0x01l -> let a, o = memop s in i16x8_load8x8_s a o
226-
| 0x02l -> let a, o = memop s in i16x8_load8x8_u a o
227-
| 0x03l -> let a, o = memop s in i32x4_load16x4_s a o
228-
| 0x04l -> let a, o = memop s in i32x4_load16x4_u a o
229-
| 0x05l -> let a, o = memop s in i64x2_load32x2_s a o
230-
| 0x06l -> let a, o = memop s in i64x2_load32x2_u a o
231-
| 0x07l -> let a, o = memop s in v8x16_load_splat a o
232-
| 0x08l -> let a, o = memop s in v16x8_load_splat a o
233-
| 0x09l -> let a, o = memop s in v32x4_load_splat a o
234-
| 0x0al -> let a, o = memop s in v64x2_load_splat a o
225+
| 0x01l -> let a, o = memop s in v128_load8x8_s a o
226+
| 0x02l -> let a, o = memop s in v128_load8x8_u a o
227+
| 0x03l -> let a, o = memop s in v128_load16x4_s a o
228+
| 0x04l -> let a, o = memop s in v128_load16x4_u a o
229+
| 0x05l -> let a, o = memop s in v128_load32x2_s a o
230+
| 0x06l -> let a, o = memop s in v128_load32x2_u a o
231+
| 0x07l -> let a, o = memop s in v128_load8_splat a o
232+
| 0x08l -> let a, o = memop s in v128_load16_splat a o
233+
| 0x09l -> let a, o = memop s in v128_load32_splat a o
234+
| 0x0al -> let a, o = memop s in v128_load64_splat a o
235235
| 0x0bl -> let a, o = memop s in v128_store a o
236236
| 0x0cl -> v128_const (at v128 s)
237237
| 0x0dl -> i8x16_shuffle (List.init 16 (fun x -> u8 s))

‎interpreter/syntax/operators.ml‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -218,25 +218,25 @@ let memory_grow = MemoryGrow
218218

219219
(* SIMD *)
220220
let v128_load align offset = SimdLoad {ty = V128Type; align; offset; sz = None}
221-
let i16x8_load8x8_s align offset =
221+
let v128_load8x8_s align offset =
222222
SimdLoad {ty = V128Type; align; offset; sz = Some (Pack64, Pack8x8 SX)}
223-
let i16x8_load8x8_u align offset =
223+
let v128_load8x8_u align offset =
224224
SimdLoad {ty = V128Type; align; offset; sz = Some (Pack64, Pack8x8 ZX)}
225-
let i32x4_load16x4_s align offset =
225+
let v128_load16x4_s align offset =
226226
SimdLoad {ty = V128Type; align; offset; sz = Some (Pack64, Pack16x4 SX)}
227-
let i32x4_load16x4_u align offset =
227+
let v128_load16x4_u align offset =
228228
SimdLoad {ty = V128Type; align; offset; sz = Some (Pack64, Pack16x4 ZX)}
229-
let i64x2_load32x2_s align offset =
229+
let v128_load32x2_s align offset =
230230
SimdLoad {ty = V128Type; align; offset; sz = Some (Pack64, Pack32x2 SX)}
231-
let i64x2_load32x2_u align offset =
231+
let v128_load32x2_u align offset =
232232
SimdLoad {ty = V128Type; align; offset; sz = Some (Pack64, Pack32x2 ZX)}
233-
let v8x16_load_splat align offset =
233+
let v128_load8_splat align offset =
234234
SimdLoad {ty= V128Type; align; offset; sz = Some (Pack8, PackSplat)}
235-
let v16x8_load_splat align offset =
235+
let v128_load16_splat align offset =
236236
SimdLoad {ty= V128Type; align; offset; sz = Some (Pack16, PackSplat)}
237-
let v32x4_load_splat align offset =
237+
let v128_load32_splat align offset =
238238
SimdLoad {ty= V128Type; align; offset; sz = Some (Pack32, PackSplat)}
239-
let v64x2_load_splat align offset =
239+
let v128_load64_splat align offset =
240240
SimdLoad {ty= V128Type; align; offset; sz = Some (Pack64, PackSplat)}
241241
let v128_store align offset = SimdStore {ty = V128Type; align; offset; sz = None}
242242

‎interpreter/text/arrange.ml‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -409,8 +409,8 @@ let cvtop = oper (IntOp.cvtop, FloatOp.cvtop, SimdOp.cvtop)
409409
let ternop = SimdOp.ternop
410410

411411
(* Temporary wart here while we finalize the names of SIMD loads and extends. *)
412-
let memop ?(type_in_name=true) name {ty; align; offset; _} sz =
413-
(if type_in_name then value_type ty ^ "." else "") ^ name ^
412+
let memop name {ty; align; offset; _} sz =
413+
value_type ty ^ "." ^ name ^
414414
(if offset = 0l then "" else " offset=" ^ nat32 offset) ^
415415
(if 1 lsl align = sz then "" else " align=" ^ nat (1 lsl align))
416416

@@ -424,18 +424,18 @@ let simd_loadop (op : simd_loadop) =
424424
match op.sz with
425425
| None -> memop "load" op (size op.ty)
426426
| Some (sz, pack_simd) ->
427-
let prefix, suffix, ext =
427+
let suffix =
428428
(match sz, pack_simd with
429-
| Pack64, Pack8x8 ext -> "i16x8", "8x8", extension ext
430-
| Pack64, Pack16x4 ext -> "i32x4", "16x4", extension ext
431-
| Pack64, Pack32x2 ext -> "i64x2", "32x2", extension ext
432-
| Pack8, PackSplat -> "v8x16", "_splat", ""
433-
| Pack16, PackSplat -> "v16x8", "_splat", ""
434-
| Pack32, PackSplat -> "v32x4", "_splat", ""
435-
| Pack64, PackSplat -> "v64x2", "_splat", ""
429+
| Pack64, Pack8x8 ext -> "8x8" ^ extension ext
430+
| Pack64, Pack16x4 ext -> "16x4" ^ extension ext
431+
| Pack64, Pack32x2 ext -> "32x2" ^ extension ext
432+
| Pack8, PackSplat -> "8_splat"
433+
| Pack16, PackSplat -> "16_splat"
434+
| Pack32, PackSplat -> "32_splat"
435+
| Pack64, PackSplat -> "64_splat"
436436
| _ -> assert false
437437
) in
438-
memop ~type_in_name:false (prefix ^ ".load" ^ suffix ^ ext) op (packed_size sz)
438+
memop ("load" ^ suffix) op (packed_size sz)
439439

440440
let storeop op =
441441
match op.sz with

‎interpreter/text/lexer.mll‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -288,20 +288,20 @@ rule token = parse
288288
(ext s i64_load8_s i64_load8_u (opt a 0))
289289
(ext s i64_load16_s i64_load16_u (opt a 1))
290290
(ext s i64_load32_s i64_load32_u (opt a 2)) o)) }
291-
| "i16x8.load8x8_"(sign as s)
292-
{ LOAD (fun a o -> (ext s i16x8_load8x8_s i16x8_load8x8_u (opt a 3)) o) }
293-
| "i32x4.load16x4_"(sign as s)
294-
{ LOAD (fun a o -> (ext s i32x4_load16x4_s i32x4_load16x4_u (opt a 3)) o) }
295-
| "i64x2.load32x2_"(sign as s)
296-
{ LOAD (fun a o -> (ext s i64x2_load32x2_s i64x2_load32x2_u (opt a 3)) o) }
297-
| "v8x16.load_splat"
298-
{ LOAD (fun a o -> (v8x16_load_splat (opt a 0)) o) }
299-
| "v16x8.load_splat"
300-
{ LOAD (fun a o -> (v16x8_load_splat (opt a 1)) o) }
301-
| "v32x4.load_splat"
302-
{ LOAD (fun a o -> (v32x4_load_splat (opt a 2)) o) }
303-
| "v64x2.load_splat"
304-
{ LOAD (fun a o -> (v64x2_load_splat (opt a 3)) o) }
291+
| "v128.load8x8_"(sign as s)
292+
{ LOAD (fun a o -> (ext s v128_load8x8_s v128_load8x8_u (opt a 3)) o) }
293+
| "v128.load16x4_"(sign as s)
294+
{ LOAD (fun a o -> (ext s v128_load16x4_s v128_load16x4_u (opt a 3)) o) }
295+
| "v128.load32x2_"(sign as s)
296+
{ LOAD (fun a o -> (ext s v128_load32x2_s v128_load32x2_u (opt a 3)) o) }
297+
| "v128.load8_splat"
298+
{ LOAD (fun a o -> (v128_load8_splat (opt a 0)) o) }
299+
| "v128.load16_splat"
300+
{ LOAD (fun a o -> (v128_load16_splat (opt a 1)) o) }
301+
| "v128.load32_splat"
302+
{ LOAD (fun a o -> (v128_load32_splat (opt a 2)) o) }
303+
| "v128.load64_splat"
304+
{ LOAD (fun a o -> (v128_load64_splat (opt a 3)) o) }
305305
| (ixx as t)".store"(mem_size as sz)
306306
{ if t = "i32" && sz = "32" then error lexbuf "unknown operator";
307307
STORE (fun a o ->

‎proposals/simd/BinarySIMD.md‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -33,16 +33,16 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive).
3333
| Instruction | `simdop` | Immediate operands |
3434
| ---------------------------|---------:|--------------------|
3535
| `v128.load` | `0x00`| m:memarg |
36-
| `i16x8.load8x8_s` | `0x01`| m:memarg |
37-
| `i16x8.load8x8_u` | `0x02`| m:memarg |
38-
| `i32x4.load16x4_s` | `0x03`| m:memarg |
39-
| `i32x4.load16x4_u` | `0x04`| m:memarg |
40-
| `i64x2.load32x2_s` | `0x05`| m:memarg |
41-
| `i64x2.load32x2_u` | `0x06`| m:memarg |
42-
| `v8x16.load_splat` | `0x07`| m:memarg |
43-
| `v16x8.load_splat` | `0x08`| m:memarg |
44-
| `v32x4.load_splat` | `0x09`| m:memarg |
45-
| `v64x2.load_splat` | `0x0a`| m:memarg |
36+
| `v128.load8x8_s` | `0x01`| m:memarg |
37+
| `v128.load8x8_u` | `0x02`| m:memarg |
38+
| `v128.load16x4_s` | `0x03`| m:memarg |
39+
| `v128.load16x4_u` | `0x04`| m:memarg |
40+
| `v128.load32x2_s` | `0x05`| m:memarg |
41+
| `v128.load32x2_u` | `0x06`| m:memarg |
42+
| `v128.load8_splat` | `0x07`| m:memarg |
43+
| `v128.load16_splat` | `0x08`| m:memarg |
44+
| `v128.load32_splat` | `0x09`| m:memarg |
45+
| `v128.load64_splat` | `0x0a`| m:memarg |
4646
| `v128.store` | `0x0b`| m:memarg |
4747
| `v128.const` | `0x0c`| i:ImmByte[16] |
4848
| `i8x16.shuffle` | `0x0d`| s:ImmLaneIdx32[16] |

‎proposals/simd/ImplementationStatus.md‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,16 @@
11
| Instruction | LLVM[1] | V8[2] | WAVM[3] | ChakraCore[4] | SpiderMonkey[5] |
22
| ---------------------------|---------------------------|--------------------|--------------------|--------------------|--------------------|
33
| `v128.load` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
4-
| `i16x8.load8x8_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
5-
| `i16x8.load8x8_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
6-
| `i32x4.load16x4_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
7-
| `i32x4.load16x4_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
8-
| `i64x2.load32x2_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
9-
| `i64x2.load32x2_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
10-
| `v8x16.load_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
11-
| `v16x8.load_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
12-
| `v32x4.load_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
13-
| `v64x2.load_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
4+
| `v128.load8x8_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
5+
| `v128.load8x8_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
6+
| `v128.load16x4_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
7+
| `v128.load16x4_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
8+
| `v128.load32x2_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
9+
| `v128.load32x2_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
10+
| `v128.load8_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
11+
| `v128.load16_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
12+
| `v128.load32_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
13+
| `v128.load64_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
1414
| `v128.store` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
1515
| `v128.const` | `-munimplemented-simd128` | :heavy_check_mark: [6] | | | :heavy_check_mark: |
1616
| `i8x16.shuffle` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |

‎proposals/simd/NewOpcodes.md‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,16 @@
11
| Memory instruction | opcode |
22
| ------------------ | ------ |
33
| v128.load | 0x00 |
4-
| i16x8.load8x8_s | 0x01 |
5-
| i16x8.load8x8_u | 0x02 |
6-
| i32x4.load16x4_s | 0x03 |
7-
| i32x4.load16x4_u | 0x04 |
8-
| i64x2.load32x2_s | 0x05 |
9-
| i64x2.load32x2_u | 0x06 |
10-
| v8x16.load_splat | 0x07 |
11-
| v16x8.load_splat | 0x08 |
12-
| v32x4.load_splat | 0x09 |
13-
| v64x2.load_splat | 0x0a |
4+
| v128.load8x8_s | 0x01 |
5+
| v128.load8x8_u | 0x02 |
6+
| v128.load16x4_s | 0x03 |
7+
| v128.load16x4_u | 0x04 |
8+
| v128.load32x2_s | 0x05 |
9+
| v128.load32x2_u | 0x06 |
10+
| v128.load8_splat | 0x07 |
11+
| v128.load16_splat | 0x08 |
12+
| v128.load32_splat | 0x09 |
13+
| v128.load64_splat | 0x0a |
1414
| v128.store | 0x0b |
1515

1616
| Basic operation | opcode |

‎proposals/simd/SIMD.md‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -768,10 +768,10 @@ def S.load(memarg):
768768

769769
### Load and Splat
770770

771-
* `v8x16.load_splat(memarg) -> v128`
772-
* `v16x8.load_splat(memarg) -> v128`
773-
* `v32x4.load_splat(memarg) -> v128`
774-
* `v64x2.load_splat(memarg) -> v128`
771+
* `v128.load8_splat(memarg) -> v128`
772+
* `v128.load16_splat(memarg) -> v128`
773+
* `v128.load32_splat(memarg) -> v128`
774+
* `v128.load64_splat(memarg) -> v128`
775775

776776
Load a single element and splat to all lanes of a `v128` vector. The natural
777777
alignment is the size of the element loaded.
@@ -784,12 +784,12 @@ def S.load_splat(memarg):
784784

785785
### Load and Extend
786786

787-
* `i16x8.load8x8_s(memarg) -> v128`: load eight 8-bit integers and sign extend each one to a 16-bit lane
788-
* `i16x8.load8x8_u(memarg) -> v128`: load eight 8-bit integers and zero extend each one to a 16-bit lane
789-
* `i32x4.load16x4_s(memarg) -> v128`: load four 16-bit integers and sign extend each one to a 32-bit lane
790-
* `i32x4.load16x4_u(memarg) -> v128`: load four 16-bit integers and zero extend each one to a 32-bit lane
791-
* `i64x2.load32x2_s(memarg) -> v128`: load two 32-bit integers and sign extend each one to a 64-bit lane
792-
* `i64x2.load32x2_u(memarg) -> v128`: load two 32-bit integers and zero extend each one to a 64-bit lane
787+
* `v128.load8x8_s(memarg) -> v128`: load eight 8-bit integers and sign extend each one to a 16-bit lane
788+
* `v128.load8x8_u(memarg) -> v128`: load eight 8-bit integers and zero extend each one to a 16-bit lane
789+
* `v128.load16x4_s(memarg) -> v128`: load four 16-bit integers and sign extend each one to a 32-bit lane
790+
* `v128.load16x4_u(memarg) -> v128`: load four 16-bit integers and zero extend each one to a 32-bit lane
791+
* `v128.load32x2_s(memarg) -> v128`: load two 32-bit integers and sign extend each one to a 64-bit lane
792+
* `v128.load32x2_u(memarg) -> v128`: load two 32-bit integers and zero extend each one to a 64-bit lane
793793

794794
Fetch consecutive integers up to 32-bit wide and produce a vector with lanes up
795795
to 64 bits. The natural alignment is 8 bytes.

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