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Commit e4fdc74

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minor update
1 parent f3c0b7d commit e4fdc74

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2 files changed

+11
-7
lines changed

2 files changed

+11
-7
lines changed

hw/rtl/VX_gpu_pkg.sv

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -86,30 +86,34 @@ package VX_gpu_pkg;
8686
} alu_mod_t;
8787

8888
typedef struct packed {
89+
logic [($bits(alu_mod_t)-`INST_FRM_BITS-`INST_FMT_BITS)-1:0] __padding;
8990
logic [`INST_FRM_BITS-1:0] frm;
9091
logic [`INST_FMT_BITS-1:0] fmt;
9192
} fpu_mod_t;
9293

9394
typedef struct packed {
95+
logic [($bits(alu_mod_t)-1-`OFFSET_BITS)-1:0] __padding;
9496
logic is_float;
9597
logic [`OFFSET_BITS-1:0] offset;
9698
} lsu_mod_t;
9799

98100
typedef struct packed {
101+
logic [($bits(alu_mod_t)-1-`VX_CSR_ADDR_BITS-5)-1:0] __padding;
99102
logic use_imm;
100103
logic [`VX_CSR_ADDR_BITS-1:0] addr;
101104
logic [4:0] imm;
102105
} csr_mod_t;
103106

104107
typedef struct packed {
108+
logic [($bits(alu_mod_t)-1)-1:0] __padding;
105109
logic is_neg;
106110
} wctl_mod_t;
107111

108112
typedef union packed {
109-
alu_mod_t alu;
110-
fpu_mod_t fpu;
111-
lsu_mod_t lsu;
112-
csr_mod_t csr;
113+
alu_mod_t alu;
114+
fpu_mod_t fpu;
115+
lsu_mod_t lsu;
116+
csr_mod_t csr;
113117
wctl_mod_t wctl;
114118
} op_mod_t;
115119

hw/rtl/core/VX_schedule.sv

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@ module VX_schedule import VX_gpu_pkg::*; #(
161161
stalled_warps_n &= ~barrier_masks[warp_ctl_if.barrier.id]; // unlock warps
162162
stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp
163163
end else begin
164-
barrier_ctrs_n[warp_ctl_if.barrier.id] = barrier_ctrs[warp_ctl_if.barrier.id] + 1;
164+
barrier_ctrs_n[warp_ctl_if.barrier.id] = barrier_ctrs[warp_ctl_if.barrier.id] + `NW_WIDTH'(1);
165165
barrier_masks_n[warp_ctl_if.barrier.id] = curr_barrier_mask_p1;
166166
end
167167
end else begin
@@ -203,7 +203,7 @@ module VX_schedule import VX_gpu_pkg::*; #(
203203

204204
// advance PC
205205
if (schedule_if_fire) begin
206-
warp_pcs_n[schedule_if.data.wid] = schedule_if.data.PC + 2;
206+
warp_pcs_n[schedule_if.data.wid] = schedule_if.data.PC + `PC_BITS'(2);
207207
end
208208
end
209209

@@ -412,7 +412,7 @@ module VX_schedule import VX_gpu_pkg::*; #(
412412
end
413413
end
414414
end
415-
`RUNTIME_ASSERT(timeout_ctr < `STALL_TIMEOUT, ("%t: *** core%0d-scheduler-timeout: stalled_warps=%b", $time, CORE_ID, stalled_warps));
415+
`RUNTIME_ASSERT(timeout_ctr < `STALL_TIMEOUT, ("%t: *** core%0d-scheduler-timeout: stalled_warps=%b", $time, CORE_ID, stalled_warps))
416416

417417
`ifdef PERF_ENABLE
418418
reg [`PERF_CTR_BITS-1:0] perf_sched_idles;

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