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tinebptinebp
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minor update
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‎hw/rtl/cache/VX_cache_bank.sv‎

Lines changed: 53 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -105,13 +105,15 @@ module VX_cache_bank #(
105105
input wire [`CS_LINE_SEL_BITS-1:0] init_line_sel
106106
);
107107

108+
localparam PIPELINE_STAGES = 2;
109+
108110
`IGNORE_UNUSED_BEGIN
109111
wire [`UP(UUID_WIDTH)-1:0] req_uuid_sel, req_uuid_st0, req_uuid_st1;
110112
`IGNORE_UNUSED_END
111113

112-
wire crsp_stall;
114+
wire crsp_queue_stall;
113115
wire mshr_alm_full;
114-
wire mreq_alm_full;
116+
wire mreq_queue_alm_full;
115117

116118
wire [`CS_LINE_ADDR_WIDTH-1:0] mem_rsp_addr;
117119

@@ -147,7 +149,7 @@ module VX_cache_bank #(
147149
wire rdw_hazard_st0;
148150
reg rdw_hazard_st1;
149151

150-
wire pipe_stall = crsp_stall || rdw_hazard_st1;
152+
wire pipe_stall = crsp_queue_stall || rdw_hazard_st1;
151153

152154
// inputs arbitration:
153155
// mshr replay has highest priority to maximize utilization since there is no miss.
@@ -169,12 +171,12 @@ module VX_cache_bank #(
169171
&& ~pipe_stall;
170172

171173
assign core_req_ready = creq_grant
172-
&& ~mreq_alm_full
174+
&& ~mreq_queue_alm_full
173175
&& ~mshr_alm_full
174176
&& ~pipe_stall;
175177

176178
wire init_fire = init_enable;
177-
wire replay_fire = replay_valid && replay_ready;
179+
wire replay_fire = replay_valid && replay_ready;
178180
wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready;
179181
wire core_req_fire = core_req_valid && core_req_ready;
180182

@@ -429,79 +431,79 @@ module VX_cache_bank #(
429431

430432
// schedule core response
431433

432-
wire crsp_valid, crsp_ready;
433-
wire [`CS_WORD_WIDTH-1:0] crsp_data;
434-
wire [REQ_SEL_WIDTH-1:0] crsp_idx;
435-
wire [TAG_WIDTH-1:0] crsp_tag;
434+
wire crsp_queue_valid, crsp_queue_ready;
435+
wire [`CS_WORD_WIDTH-1:0] crsp_queue_data;
436+
wire [REQ_SEL_WIDTH-1:0] crsp_queue_idx;
437+
wire [TAG_WIDTH-1:0] crsp_queue_tag;
436438

437-
assign crsp_valid = do_read_hit_st1 || do_replay_rd_st1;
438-
assign crsp_idx = req_idx_st1;
439-
assign crsp_data = read_data_st1;
440-
assign crsp_tag = tag_st1;
439+
assign crsp_queue_valid = do_read_hit_st1 || do_replay_rd_st1;
440+
assign crsp_queue_idx = req_idx_st1;
441+
assign crsp_queue_data = read_data_st1;
442+
assign crsp_queue_tag = tag_st1;
441443

442-
`RESET_RELAY (crsp_reset, reset);
444+
`RESET_RELAY (crsp_queue_reset, reset);
443445

444446
VX_elastic_buffer #(
445447
.DATAW (TAG_WIDTH + `CS_WORD_WIDTH + REQ_SEL_WIDTH),
446448
.SIZE (CRSQ_SIZE),
447449
.OUT_REG (`TO_OUT_BUF_REG(CORE_OUT_BUF))
448450
) core_rsp_queue (
449451
.clk (clk),
450-
.reset (crsp_reset),
451-
.valid_in (crsp_valid && ~rdw_hazard_st1),
452-
.ready_in (crsp_ready),
453-
.data_in ({crsp_tag, crsp_data, crsp_idx}),
452+
.reset (crsp_queue_reset),
453+
.valid_in (crsp_queue_valid && ~rdw_hazard_st1),
454+
.ready_in (crsp_queue_ready),
455+
.data_in ({crsp_queue_tag, crsp_queue_data, crsp_queue_idx}),
454456
.data_out ({core_rsp_tag, core_rsp_data, core_rsp_idx}),
455457
.valid_out (core_rsp_valid),
456458
.ready_out (core_rsp_ready)
457459
);
458460

459-
assign crsp_stall = crsp_valid && ~crsp_ready;
461+
assign crsp_queue_stall = crsp_queue_valid && ~crsp_queue_ready;
460462

461463
// schedule memory request
462464

463-
wire mreq_push, mreq_pop, mreq_empty;
464-
wire [`CS_WORD_WIDTH-1:0] mreq_data;
465-
wire [WORD_SIZE-1:0] mreq_byteen;
466-
wire [WORD_SEL_WIDTH-1:0] mreq_wsel;
467-
wire [`CS_LINE_ADDR_WIDTH-1:0] mreq_addr;
468-
wire [MSHR_ADDR_WIDTH-1:0] mreq_id;
469-
wire mreq_rw;
465+
wire mreq_queue_push, mreq_queue_pop, mreq_queue_empty;
466+
wire [`CS_WORD_WIDTH-1:0] mreq_queue_data;
467+
wire [WORD_SIZE-1:0] mreq_queue_byteen;
468+
wire [WORD_SEL_WIDTH-1:0] mreq_queue_wsel;
469+
wire [`CS_LINE_ADDR_WIDTH-1:0] mreq_queue_addr;
470+
wire [MSHR_ADDR_WIDTH-1:0] mreq_queue_id;
471+
wire mreq_queue_rw;
470472

471-
assign mreq_push = (do_read_miss_st1 && ~mshr_pending_st1)
472-
|| do_creq_wr_st1;
473+
assign mreq_queue_push = (do_read_miss_st1 && ~mshr_pending_st1)
474+
|| do_creq_wr_st1;
473475

474-
assign mreq_pop = mem_req_valid && mem_req_ready;
476+
assign mreq_queue_pop = mem_req_valid && mem_req_ready;
475477

476-
assign mreq_rw = WRITE_ENABLE && rw_st1;
477-
assign mreq_addr = addr_st1;
478-
assign mreq_id = mshr_id_st1;
479-
assign mreq_wsel = wsel_st1;
480-
assign mreq_byteen = byteen_st1;
481-
assign mreq_data = write_data_st1;
478+
assign mreq_queue_rw = WRITE_ENABLE && rw_st1;
479+
assign mreq_queue_addr = addr_st1;
480+
assign mreq_queue_id = mshr_id_st1;
481+
assign mreq_queue_wsel = wsel_st1;
482+
assign mreq_queue_byteen = byteen_st1;
483+
assign mreq_queue_data = write_data_st1;
482484

483-
`RESET_RELAY (mreq_reset, reset);
485+
`RESET_RELAY (mreq_queue_reset, reset);
484486

485487
VX_fifo_queue #(
486488
.DATAW (1 + `CS_LINE_ADDR_WIDTH + MSHR_ADDR_WIDTH + WORD_SIZE + WORD_SEL_WIDTH + `CS_WORD_WIDTH),
487489
.DEPTH (MREQ_SIZE),
488-
.ALM_FULL (MREQ_SIZE-2),
490+
.ALM_FULL (MREQ_SIZE-PIPELINE_STAGES),
489491
.OUT_REG (`TO_OUT_BUF_REG(MEM_OUT_BUF))
490492
) mem_req_queue (
491493
.clk (clk),
492-
.reset (mreq_reset),
493-
.push (mreq_push),
494-
.pop (mreq_pop),
495-
.data_in ({mreq_rw, mreq_addr, mreq_id, mreq_byteen, mreq_wsel, mreq_data}),
494+
.reset (mreq_queue_reset),
495+
.push (mreq_queue_push),
496+
.pop (mreq_queue_pop),
497+
.data_in ({mreq_queue_rw, mreq_queue_addr, mreq_queue_id, mreq_queue_byteen, mreq_queue_wsel, mreq_queue_data}),
496498
.data_out ({mem_req_rw, mem_req_addr, mem_req_id, mem_req_byteen, mem_req_wsel, mem_req_data}),
497-
.empty (mreq_empty),
498-
.alm_full (mreq_alm_full),
499+
.empty (mreq_queue_empty),
500+
.alm_full (mreq_queue_alm_full),
499501
`UNUSED_PIN (full),
500502
`UNUSED_PIN (alm_empty),
501503
`UNUSED_PIN (size)
502504
);
503505

504-
assign mem_req_valid = ~mreq_empty;
506+
assign mem_req_valid = ~mreq_queue_empty;
505507

506508
///////////////////////////////////////////////////////////////////////////////
507509

@@ -512,12 +514,12 @@ module VX_cache_bank #(
512514
`endif
513515

514516
`ifdef DBG_TRACE_CACHE
515-
wire crsp_fire = crsp_valid && crsp_ready;
517+
wire crsp_queue_fire = crsp_queue_valid && crsp_queue_ready;
516518
wire pipeline_stall = (replay_valid || mem_rsp_valid || core_req_valid)
517519
&& ~(replay_fire || mem_rsp_fire || core_req_fire);
518520
always @(posedge clk) begin
519521
if (pipeline_stall) begin
520-
`TRACE(3, ("%d: *** %s-bank%0d stall: crsq=%b, mreq=%b, mshr=%b\n", $time, INSTANCE_ID, BANK_ID, crsp_stall, mreq_alm_full, mshr_alm_full));
522+
`TRACE(3, ("%d: *** %s-bank%0d stall: crsq=%b, mreq=%b, mshr=%b\n", $time, INSTANCE_ID, BANK_ID, crsp_queue_stall, mreq_queue_alm_full, mshr_alm_full));
521523
end
522524
if (init_enable) begin
523525
`TRACE(2, ("%d: %s-bank%0d init: addr=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(init_line_sel, BANK_ID)));
@@ -534,14 +536,14 @@ module VX_cache_bank #(
534536
else
535537
`TRACE(2, ("%d: %s-bank%0d core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, req_uuid_sel));
536538
end
537-
if (crsp_fire) begin
538-
`TRACE(2, ("%d: %s-bank%0d core-rd-rsp: addr=0x%0h, tag=0x%0h, req_idx=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(addr_st1, BANK_ID), crsp_tag, crsp_idx, crsp_data, req_uuid_st1));
539+
if (crsp_queue_fire) begin
540+
`TRACE(2, ("%d: %s-bank%0d core-rd-rsp: addr=0x%0h, tag=0x%0h, req_idx=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(addr_st1, BANK_ID), crsp_queue_tag, crsp_queue_idx, crsp_queue_data, req_uuid_st1));
539541
end
540-
if (mreq_push) begin
542+
if (mreq_queue_push) begin
541543
if (do_creq_wr_st1)
542-
`TRACE(2, ("%d: %s-bank%0d writethrough: addr=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_addr, BANK_ID), mreq_byteen, mreq_data, req_uuid_st1));
544+
`TRACE(2, ("%d: %s-bank%0d writethrough: addr=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_queue_addr, BANK_ID), mreq_queue_byteen, mreq_queue_data, req_uuid_st1));
543545
else
544-
`TRACE(2, ("%d: %s-bank%0d fill-req: addr=0x%0h, mshr_id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_addr, BANK_ID), mreq_id, req_uuid_st1));
546+
`TRACE(2, ("%d: %s-bank%0d fill-req: addr=0x%0h, mshr_id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_queue_addr, BANK_ID), mreq_queue_id, req_uuid_st1));
545547
end
546548
end
547549
`endif

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