+ support for ZICOND RISC-V extension

+ RTL decode refactoring

Author: tinebp

ci/trace_csv.py

@@ -1,12 +1,12 @@
 #!/usr/bin/env python3
 
 # Copyright © 2019-2023
-# 
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 # http://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -17,15 +17,15 @@
 import argparse
 import csv
 import re
-            
+
 def parse_args():
     parser = argparse.ArgumentParser(description='CPU trace log to CSV format converter.')
     parser.add_argument('-t', '--type', default='simx', help='log type (rtlsim or simx)')
     parser.add_argument('-o', '--csv', default='trace.csv', help='Output CSV file')
     parser.add_argument('log', help='Input log file')
     return parser.parse_args()
 
-def parse_simx(log_filename):    
+def parse_simx(log_filename):
     pc_pattern = r"PC=(0x[0-9a-fA-F]+)"
     instr_pattern = r"Instr (0x[0-9a-fA-F]+):"
     opcode_pattern = r"Instr 0x[0-9a-fA-F]+: ([0-9a-zA-Z_\.]+)"
@@ -42,12 +42,12 @@ def parse_simx(log_filename):
             if line.startswith("DEBUG Fetch:"):
                 if instr_data:
                     entries.append(instr_data)
-                instr_data = {}                       
+                instr_data = {}
                 instr_data["lineno"] = lineno
                 instr_data["PC"] = re.search(pc_pattern, line).group(1)
                 instr_data["core_id"] = re.search(core_id_pattern, line).group(1)
                 instr_data["warp_id"] = re.search(warp_id_pattern, line).group(1)
-                instr_data["tmask"] = re.search(tmask_pattern, line).group(1)            
+                instr_data["tmask"] = re.search(tmask_pattern, line).group(1)
                 instr_data["uuid"] = re.search(uuid_pattern, line).group(1)
             elif line.startswith("DEBUG Instr"):
                 instr_data["instr"] = re.search(instr_pattern, line).group(1)
@@ -60,13 +60,13 @@ def parse_simx(log_filename):
         if instr_data:
             entries.append(instr_data)
     return entries
-        
+
 def reverse_binary(bin_str):
     return bin_str[::-1]
 
 def bin_to_array(bin_str):
     return [int(bit) for bit in bin_str]
-        
+
 def append_reg(text, value, sep):
     if sep:
         text += ", "
@@ -77,14 +77,7 @@ def append_reg(text, value, sep):
         text += "x" + value
     sep = True
     return text, sep
-        
-def append_imm(text, value, sep):    
-    if sep:
-        text += ", "
-    text += value
-    sep = True
-    return text, sep
-    
+
 def append_value(text, reg, value, tmask_arr, sep):
     text, sep = append_reg(text, reg, sep)
     text += "={"
@@ -97,8 +90,8 @@ def append_value(text, reg, value, tmask_arr, sep):
             text +="-"
     text += "}"
     return text, sep
-        
-def parse_rtlsim(log_filename):    
+
+def parse_rtlsim(log_filename):
     line_pattern = r"\d+: core(\d+)-(decode|issue|commit)"
     pc_pattern = r"PC=(0x[0-9a-fA-F]+)"
     instr_pattern = r"instr=(0x[0-9a-fA-F]+)"
@@ -108,8 +101,6 @@ def parse_rtlsim(log_filename):
     tmask_pattern = r"tmask=(\d+)"
     wb_pattern = r"wb=(\d)"
     opds_pattern = r"opds=(\d+)"
-    use_imm_pattern = r"use_imm=(\d)"
-    imm_pattern = r"imm=(0x[0-9a-fA-F]+)"
     rd_pattern = r"rd=(\d+)"
     rs1_pattern = r"rs1=(\d+)"
     rs2_pattern = r"rs2=(\d+)"
@@ -120,24 +111,24 @@ def parse_rtlsim(log_filename):
     rd_data_pattern = r"data=\{(.+?)\}"
     eop_pattern = r"eop=(\d)"
     uuid_pattern = r"#(\d+)"
-    entries = []    
+    entries = []
     with open(log_filename, 'r') as log_file:
         instr_data = {}
         for lineno, line in enumerate(log_file, start=1):
             line_match = re.search(line_pattern, line)
             if line_match:
                 PC = re.search(pc_pattern, line).group(1)
-                warp_id = re.search(warp_id_pattern, line).group(1)    
+                warp_id = re.search(warp_id_pattern, line).group(1)
                 tmask = re.search(tmask_pattern, line).group(1)
-                uuid = re.search(uuid_pattern, line).group(1)            
+                uuid = re.search(uuid_pattern, line).group(1)
                 core_id = line_match.group(1)
                 stage = line_match.group(2)
-                if stage == "decode":                
+                if stage == "decode":
                     trace = {}
                     trace["uuid"] = uuid
-                    trace["PC"] = PC                
+                    trace["PC"] = PC
                     trace["core_id"] = core_id
-                    trace["warp_id"] = warp_id    
+                    trace["warp_id"] = warp_id
                     trace["tmask"] = reverse_binary(tmask)
                     trace["instr"] = re.search(instr_pattern, line).group(1)
                     trace["opcode"] = re.search(op_pattern, line).group(1)
@@ -146,8 +137,6 @@ def parse_rtlsim(log_filename):
                     trace["rs1"] = re.search(rs1_pattern, line).group(1)
                     trace["rs2"] = re.search(rs2_pattern, line).group(1)
                     trace["rs3"] = re.search(rs3_pattern, line).group(1)
-                    trace["use_imm"] = re.search(use_imm_pattern, line).group(1) == "1"
-                    trace["imm"] = re.search(imm_pattern, line).group(1)
                     instr_data[uuid] = trace
                 elif stage == "issue":
                     if uuid in instr_data:
@@ -162,7 +151,7 @@ def parse_rtlsim(log_filename):
                             trace["rs3_data"] = re.search(rs3_data_pattern, line).group(1).split(', ')[::-1]
                         trace["issued"] = True
                         instr_data[uuid] = trace
-                elif stage == "commit":     
+                elif stage == "commit":
                     if uuid in instr_data:
                         trace = instr_data[uuid]
                         if "issued" in trace:
@@ -205,16 +194,14 @@ def parse_rtlsim(log_filename):
                                 del trace["rs1"]
                                 del trace["rs2"]
                                 del trace["rs3"]
-                                del trace["use_imm"]
-                                del trace["imm"]   
-                                del trace["issued"]                     
+                                del trace["issued"]
                                 del instr_data[uuid]
                                 entries.append(trace)
-    return entries                            
+    return entries
 
 def write_csv(log_filename, csv_filename, log_type):
     entries = None
-    
+
     # parse log file
     if log_type == "rtlsim":
         entries = parse_rtlsim(log_filename)
@@ -223,19 +210,19 @@ def write_csv(log_filename, csv_filename, log_type):
     else:
         print('Error: invalid log type')
         sys.exit()
-        
+
     # sort entries by uuid
     entries.sort(key=lambda x: (int(x['uuid'])))
     for entry in entries:
         del entry['lineno']
-    
+
     # write to CSV
     with open(csv_filename, 'w', newline='') as csv_file:
         fieldnames = ["uuid", "PC", "opcode", "instr", "core_id", "warp_id", "tmask", "operands", "destination"]
         writer = csv.DictWriter(csv_file, fieldnames=fieldnames)
         writer.writeheader()
         for entry in entries:
-            writer.writerow(entry)    
+            writer.writerow(entry)
 
 def main():
     args = parse_args()

hw/rtl/VX_config.vh

@@ -40,6 +40,10 @@
 `define EXT_F_ENABLE
 `endif
 
+`ifndef EXT_ZICOND_ENABLE
+`define EXT_ZICOND_ENABLE
+`endif
+
 `ifndef XLEN_32
 `ifndef XLEN_64
 `define XLEN_32
@@ -637,6 +641,12 @@
     `define EXT_M_ENABLED   0
 `endif
 
+`ifdef EXT_ZICOND_ENABLE
+    `define EXT_ZICOND_ENABLED 1
+`else
+    `define EXT_ZICOND_ENABLED 0
+`endif
+
 `define ISA_STD_A           0
 `define ISA_STD_C           2
 `define ISA_STD_D           3
@@ -654,12 +664,14 @@
 `define ISA_EXT_L2CACHE     2
 `define ISA_EXT_L3CACHE     3
 `define ISA_EXT_LMEM        4
+`define ISA_EXT_ZICOND      5
 
 `define MISA_EXT  (`ICACHE_ENABLED  << `ISA_EXT_ICACHE) \
                 | (`DCACHE_ENABLED  << `ISA_EXT_DCACHE) \
                 | (`L2_ENABLED      << `ISA_EXT_L2CACHE) \
                 | (`L3_ENABLED      << `ISA_EXT_L3CACHE) \
-                | (`LMEM_ENABLED    << `ISA_EXT_LMEM)
+                | (`LMEM_ENABLED    << `ISA_EXT_LMEM) \
+                | (`EXT_ZICOND_ENABLED << `ISA_EXT_ZICOND)
 
 `define MISA_STD  (`EXT_A_ENABLED <<  0) /* A - Atomic Instructions extension */ \
                 | (0 <<  1) /* B - Tentatively reserved for Bit operations extension */ \

hw/rtl/VX_define.vh

@@ -55,6 +55,10 @@
 `define UUID_WIDTH      1
 `endif
 
+`define PC_BITS         (`XLEN-1)
+`define OFFSET_BITS     12
+`define IMM_BITS        `XLEN
+
 ///////////////////////////////////////////////////////////////////////////////
 
 `define EX_ALU          0
@@ -105,6 +109,10 @@
 `define INST_EXT3       7'b1011011 // 0x5B
 `define INST_EXT4       7'b1111011 // 0x7B
 
+// Opcode extensions
+`define INST_R_F7_MUL   7'b0000001
+`define INST_R_F7_ZICOND 7'b0000111
+
 ///////////////////////////////////////////////////////////////////////////////
 
 `define INST_FRM_RNE    3'b000  // round to nearest even
@@ -118,7 +126,7 @@
 ///////////////////////////////////////////////////////////////////////////////
 
 `define INST_OP_BITS    4
-`define INST_MOD_BITS   3
+`define INST_MOD_BITS   $bits(op_mod_t)
 `define INST_FMT_BITS   2
 
 ///////////////////////////////////////////////////////////////////////////////
@@ -135,14 +143,23 @@
 `define INST_ALU_OR          4'b1101
 `define INST_ALU_XOR         4'b1110
 `define INST_ALU_SLL         4'b1111
-`define INST_ALU_OTHER       4'b0111
+`define INST_ALU_CZEQ        4'b1010
+`define INST_ALU_CZNE        4'b1011
+//`define INST_ALU_UNUSED    4'b0001
+//`define INST_ALU_UNUSED    4'b0110
+
+
+`define ALU_TYPE_BITS        2
+`define ALU_TYPE_ARITH       0
+`define ALU_TYPE_BRANCH      1
+`define ALU_TYPE_MULDIV      2
+`define ALU_TYPE_OTHER       3
+
 `define INST_ALU_BITS        4
 `define INST_ALU_CLASS(op)   op[3:2]
 `define INST_ALU_SIGNED(op)  op[0]
 `define INST_ALU_IS_SUB(op)  op[1]
-`define INST_ALU_IS_BR(mod)  mod[0]
-`define INST_ALU_IS_M(mod)   mod[1]
-`define INST_ALU_IS_W(mod)   mod[2]
+`define INST_ALU_IS_CZERO(op) (op[3:1] == 3'b101)
 
 `define INST_BR_EQ           4'b0000
 `define INST_BR_NE           4'b0010
@@ -225,9 +242,8 @@
 `define INST_FPU_NMSUB       4'b1110
 `define INST_FPU_NMADD       4'b1111
 `define INST_FPU_BITS        4
-`define INST_FPU_IS_W(mod)   (mod[4])
-`define INST_FPU_IS_CLASS(op, mod) (op == `INST_FPU_MISC && mod == 3)
-`define INST_FPU_IS_MVXW(op, mod) (op == `INST_FPU_MISC && mod == 4)
+`define INST_FPU_IS_CLASS(op, frm) (op == `INST_FPU_MISC && frm == 3)
+`define INST_FPU_IS_MVXW(op, frm) (op == `INST_FPU_MISC && frm == 4)
 
 `define INST_SFU_TMC         4'h0
 `define INST_SFU_WSPAWN      4'h1
@@ -238,7 +254,6 @@
 `define INST_SFU_CSRRW       4'h6
 `define INST_SFU_CSRRS       4'h7
 `define INST_SFU_CSRRC       4'h8
-`define INST_SFU_CMOV        4'h9
 `define INST_SFU_BITS        4
 `define INST_SFU_CSR(f3)     (4'h6 + 4'(f3) - 4'h1)
 `define INST_SFU_IS_WCTL(op) (op <= 5)
@@ -414,13 +429,10 @@
     data.uuid, \
     data.wis, \
     data.tmask, \
+    data.PC, \
     data.op_type, \
     data.op_mod, \
     data.wb, \
-    data.use_PC, \
-    data.use_imm, \
-    data.PC, \
-    data.imm, \
     data.rd, \
     tid, \
     data.rs1_data, \

hw/rtl/VX_gpu_pkg.sv

@@ -26,15 +26,15 @@ package VX_gpu_pkg;
     typedef struct packed {
         logic                   valid;
         logic [`NUM_WARPS-1:0]  wmask;
-        logic [`XLEN-1:0]       pc;
+        logic [`PC_BITS-1:0]    pc;
     } wspawn_t;
 
     typedef struct packed {
         logic                    valid;
         logic                    is_dvg;
         logic [`NUM_THREADS-1:0] then_tmask;
         logic [`NUM_THREADS-1:0] else_tmask;
-        logic [`XLEN-1:0]        next_pc;
+        logic [`PC_BITS-1:0]     next_pc;
     } split_t;
 
     typedef struct packed {
@@ -55,9 +55,9 @@ package VX_gpu_pkg;
     } barrier_t;
 
     typedef struct packed {
-        logic [`XLEN-1:0]   startup_addr;
-        logic [`XLEN-1:0]   startup_arg;
-        logic [7:0]         mpm_class;
+        logic [`XLEN-1:0]       startup_addr;
+        logic [`XLEN-1:0]       startup_arg;
+        logic [7:0]             mpm_class;
     } base_dcrs_t;
 
     typedef struct packed {
@@ -77,6 +77,42 @@ package VX_gpu_pkg;
         logic [`PERF_CTR_BITS-1:0] latency;
     } mem_perf_t;
 
+    typedef struct packed {
+        logic use_PC;
+        logic use_imm;
+        logic is_w;
+        logic [`ALU_TYPE_BITS-1:0] xtype;
+        logic [`IMM_BITS-1:0] imm;
+    } alu_mod_t;
+
+    typedef struct packed {
+        logic [`INST_FRM_BITS-1:0] frm;
+        logic [`INST_FMT_BITS-1:0] fmt;
+    } fpu_mod_t;
+
+    typedef struct packed {
+        logic is_float;
+        logic [`OFFSET_BITS-1:0] offset;
+    } lsu_mod_t;
+
+    typedef struct packed {
+        logic use_imm;
+        logic [`VX_CSR_ADDR_BITS-1:0] addr;
+        logic [4:0] imm;
+    } csr_mod_t;
+
+    typedef struct packed {
+        logic is_neg;
+    } wctl_mod_t;
+
+    typedef union packed {
+        alu_mod_t alu;
+        fpu_mod_t fpu;
+        lsu_mod_t lsu;
+        csr_mod_t csr;
+        wctl_mod_t wctl;
+    } op_mod_t;
+
     /* verilator lint_off UNUSED */
 
     ///////////////////////// LSU memory Parameters ///////////////////////////