@@ -1021,25 +1021,25 @@ void kgd_gfx_v10_get_iq_wait_times(struct amdgpu_device *adev,
10211021 * wait_times = RREG32 (SOC15_REG_OFFSET (GC , 0 , mmCP_IQ_WAIT_TIME2 ));
10221022}
10231023
1024- void kgd_gfx_v10_build_grace_period_packet_info (struct amdgpu_device * adev ,
1024+ void kgd_gfx_v10_build_dequeue_wait_counts_packet_info (struct amdgpu_device * adev ,
10251025 uint32_t wait_times ,
1026- uint32_t grace_period ,
1026+ uint32_t sch_wave ,
1027+ uint32_t que_sleep ,
10271028 uint32_t * reg_offset ,
10281029 uint32_t * reg_data )
10291030{
10301031 * reg_data = wait_times ;
10311032
1032- /*
1033- * The CP cannont handle a 0 grace period input and will result in
1034- * an infinite grace period being set so set to 1 to prevent this.
1035- */
1036- if (grace_period == 0 )
1037- grace_period = 1 ;
1038-
1039- * reg_data = REG_SET_FIELD (* reg_data ,
1040- CP_IQ_WAIT_TIME2 ,
1041- SCH_WAVE ,
1042- grace_period );
1033+ if (sch_wave )
1034+ * reg_data = REG_SET_FIELD (* reg_data ,
1035+ CP_IQ_WAIT_TIME2 ,
1036+ SCH_WAVE ,
1037+ sch_wave );
1038+ if (que_sleep )
1039+ * reg_data = REG_SET_FIELD (* reg_data ,
1040+ CP_IQ_WAIT_TIME2 ,
1041+ QUE_SLEEP ,
1042+ que_sleep );
10431043
10441044 * reg_offset = SOC15_REG_OFFSET (GC , 0 , mmCP_IQ_WAIT_TIME2 );
10451045}
@@ -1115,7 +1115,7 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
11151115 .set_address_watch = kgd_gfx_v10_set_address_watch ,
11161116 .clear_address_watch = kgd_gfx_v10_clear_address_watch ,
11171117 .get_iq_wait_times = kgd_gfx_v10_get_iq_wait_times ,
1118- .build_grace_period_packet_info = kgd_gfx_v10_build_grace_period_packet_info ,
1118+ .build_dequeue_wait_counts_packet_info = kgd_gfx_v10_build_dequeue_wait_counts_packet_info ,
11191119 .program_trap_handler_settings = program_trap_handler_settings ,
11201120 .hqd_get_pq_addr = kgd_gfx_v10_hqd_get_pq_addr ,
11211121 .hqd_reset = kgd_gfx_v10_hqd_reset ,
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