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bjorn-helgaasbjorn-helgaas
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Merge branch 'pci/controller/qcom'
- Enable MSI interrupts if 'global' IRQ is supported, since a previous commit unintentionally masked them (Manivannan Sadhasivam) - Move endpoint controller cleanups that depend on refclk from the host to the notifier that tells us the host has deasserted PERST# (Manivannan Sadhasivam) - Add DT binding and driver support for IPQ9574, with Synopsys IP v5.80a and Qcom IP 1.27.0 (devi priya) - Move the OPP "operating-points-v2" table from the qcom,pcie-sm8450.yaml DT binding to qcom,pcie-common.yaml, where it can be used by other Qcom platforms (Qiang Yu) - Add 'global' SPI interrupt for events like link-up, link-down to qcom,pcie-x1e80100 DT binding so we can start enumeration when the link comes up (Qiang Yu) - Disable ASPM L0s for qcom,pcie-x1e80100 since the PHY is not tuned to support this (Qiang Yu) - Add ops_1_21_0 for SC8280X family SoC, which doesn't use the 'iommu-map' DT property and doesn't need BDF-to-SID translation (Qiang Yu) * pci/controller/qcom: PCI: qcom: Disable ASPM L0s for X1E80100 PCI: qcom: Remove BDF2SID mapping config for SC8280X family SoC dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt dt-bindings: PCI: qcom: Move OPP table to qcom,pcie-common.yaml PCI: qcom: Add support for IPQ9574 dt-bindings: PCI: qcom: Document the IPQ9574 PCIe controller PCI: qcom-ep: Move controller cleanups to qcom_pcie_perst_deassert() PCI: qcom: Enable MSI interrupts together with Link up if 'Global IRQ' is supported
2 parents 7b5d234 + fba6045 commit f54ff40

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‎Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,10 @@ properties:
8181
vddpe-3v3-supply:
8282
description: PCIe endpoint power supply
8383

84+
operating-points-v2: true
85+
opp-table:
86+
type: object
87+
8488
required:
8589
- reg
8690
- reg-names

‎Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -70,10 +70,6 @@ properties:
7070
- const: msi7
7171
- const: global
7272

73-
operating-points-v2: true
74-
opp-table:
75-
type: object
76-
7773
resets:
7874
maxItems: 1
7975

‎Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -47,9 +47,10 @@ properties:
4747

4848
interrupts:
4949
minItems: 8
50-
maxItems: 8
50+
maxItems: 9
5151

5252
interrupt-names:
53+
minItems: 8
5354
items:
5455
- const: msi0
5556
- const: msi1
@@ -59,6 +60,7 @@ properties:
5960
- const: msi5
6061
- const: msi6
6162
- const: msi7
63+
- const: global
6264

6365
resets:
6466
minItems: 1
@@ -130,9 +132,10 @@ examples:
130132
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
131133
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
132134
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
133-
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
135+
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
136+
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
134137
interrupt-names = "msi0", "msi1", "msi2", "msi3",
135-
"msi4", "msi5", "msi6", "msi7";
138+
"msi4", "msi5", "msi6", "msi7", "global";
136139
#interrupt-cells = <1>;
137140
interrupt-map-mask = <0 0 0 0x7>;
138141
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

‎Documentation/devicetree/bindings/pci/qcom,pcie.yaml‎

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ properties:
2626
- qcom,pcie-ipq8064-v2
2727
- qcom,pcie-ipq8074
2828
- qcom,pcie-ipq8074-gen3
29+
- qcom,pcie-ipq9574
2930
- qcom,pcie-msm8996
3031
- qcom,pcie-qcs404
3132
- qcom,pcie-sdm845
@@ -164,6 +165,7 @@ allOf:
164165
enum:
165166
- qcom,pcie-ipq6018
166167
- qcom,pcie-ipq8074-gen3
168+
- qcom,pcie-ipq9574
167169
then:
168170
properties:
169171
reg:
@@ -400,6 +402,53 @@ allOf:
400402
- const: axi_m_sticky # AXI Master Sticky reset
401403
- const: axi_s_sticky # AXI Slave Sticky reset
402404

405+
- if:
406+
properties:
407+
compatible:
408+
contains:
409+
enum:
410+
- qcom,pcie-ipq9574
411+
then:
412+
properties:
413+
clocks:
414+
minItems: 6
415+
maxItems: 6
416+
clock-names:
417+
items:
418+
- const: axi_m # AXI Master clock
419+
- const: axi_s # AXI Slave clock
420+
- const: axi_bridge
421+
- const: rchng
422+
- const: ahb
423+
- const: aux
424+
425+
resets:
426+
minItems: 8
427+
maxItems: 8
428+
reset-names:
429+
items:
430+
- const: pipe # PIPE reset
431+
- const: sticky # Core Sticky reset
432+
- const: axi_s_sticky # AXI Slave Sticky reset
433+
- const: axi_s # AXI Slave reset
434+
- const: axi_m_sticky # AXI Master Sticky reset
435+
- const: axi_m # AXI Master reset
436+
- const: aux # AUX Reset
437+
- const: ahb # AHB Reset
438+
439+
interrupts:
440+
minItems: 8
441+
interrupt-names:
442+
items:
443+
- const: msi0
444+
- const: msi1
445+
- const: msi2
446+
- const: msi3
447+
- const: msi4
448+
- const: msi5
449+
- const: msi6
450+
- const: msi7
451+
403452
- if:
404453
properties:
405454
compatible:
@@ -510,6 +559,7 @@ allOf:
510559
- qcom,pcie-ipq8064v2
511560
- qcom,pcie-ipq8074
512561
- qcom,pcie-ipq8074-gen3
562+
- qcom,pcie-ipq9574
513563
- qcom,pcie-qcs404
514564
then:
515565
required:

‎drivers/pci/controller/dwc/pcie-qcom-ep.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -396,6 +396,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
396396
return ret;
397397
}
398398

399+
/* Perform cleanup that requires refclk */
400+
pci_epc_deinit_notify(pci->ep.epc);
401+
dw_pcie_ep_cleanup(&pci->ep);
402+
399403
/* Assert WAKE# to RC to indicate device is ready */
400404
gpiod_set_value_cansleep(pcie_ep->wake, 1);
401405
usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500);
@@ -540,8 +544,6 @@ static void qcom_pcie_perst_assert(struct dw_pcie *pci)
540544
{
541545
struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
542546

543-
pci_epc_deinit_notify(pci->ep.epc);
544-
dw_pcie_ep_cleanup(&pci->ep);
545547
qcom_pcie_disable_resources(pcie_ep);
546548
pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
547549
}

‎drivers/pci/controller/dwc/pcie-qcom.c‎

Lines changed: 16 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,7 @@
133133

134134
/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
135135
#define PARF_INT_ALL_LINK_UP BIT(13)
136+
#define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23)
136137

137138
/* PARF_NO_SNOOP_OVERIDE register fields */
138139
#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
@@ -1364,6 +1365,16 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
13641365
.config_sid = qcom_pcie_config_sid_1_9_0,
13651366
};
13661367

1368+
/* Qcom IP rev.: 1.21.0 Synopsys IP rev.: 5.60a */
1369+
static const struct qcom_pcie_ops ops_1_21_0 = {
1370+
.get_resources = qcom_pcie_get_resources_2_7_0,
1371+
.init = qcom_pcie_init_2_7_0,
1372+
.post_init = qcom_pcie_post_init_2_7_0,
1373+
.host_post_init = qcom_pcie_host_post_init_2_7_0,
1374+
.deinit = qcom_pcie_deinit_2_7_0,
1375+
.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1376+
};
1377+
13671378
/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
13681379
static const struct qcom_pcie_ops ops_2_9_0 = {
13691380
.get_resources = qcom_pcie_get_resources_2_9_0,
@@ -1411,7 +1422,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
14111422
};
14121423

14131424
static const struct qcom_pcie_cfg cfg_sc8280xp = {
1414-
.ops = &ops_1_9_0,
1425+
.ops = &ops_1_21_0,
14151426
.no_l0s = true,
14161427
};
14171428

@@ -1716,7 +1727,8 @@ static int qcom_pcie_probe(struct platform_device *pdev)
17161727
goto err_host_deinit;
17171728
}
17181729

1719-
writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK);
1730+
writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_MSI_DEV_0_7,
1731+
pcie->parf + PARF_INT_ALL_MASK);
17201732
}
17211733

17221734
qcom_pcie_icc_opp_update(pcie);
@@ -1828,6 +1840,7 @@ static const struct of_device_id qcom_pcie_match[] = {
18281840
{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
18291841
{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
18301842
{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
1843+
{ .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 },
18311844
{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
18321845
{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
18331846
{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
@@ -1843,7 +1856,7 @@ static const struct of_device_id qcom_pcie_match[] = {
18431856
{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
18441857
{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
18451858
{ .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
1846-
{ .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 },
1859+
{ .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp },
18471860
{ }
18481861
};
18491862

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