drm/exynos: exynos7_drm_decon: fix ideal_clk by converting it to Hz

Kaustabh Chakraborty · daeinki · commit f3cb045e2603 · 2024-11-04T10:50:46.000+09:00
The clkdiv values are incorrect as ideal_clk is in kHz and the clock
rate of vclk is in Hz. Multiply 1000 to ideal_clk to bring it to Hz.

Signed-off-by: Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;
Signed-off-by: Inki Dae &lt;inki.dae@samsung.com&gt;
diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
@@ -137,7 +137,7 @@ static void decon_ctx_remove(struct decon_context *ctx)
 static u32 decon_calc_clkdiv(struct decon_context *ctx,
 		const struct drm_display_mode *mode)
 {
-	unsigned long ideal_clk = mode->clock;
+	unsigned long ideal_clk = mode->clock * 1000;
 	u32 clkdiv;
 
 	/* Find the clock divider value that gets us closest to ideal_clk */

Original file line number	Diff line number	Diff line change
`@@ -137,7 +137,7 @@ static void decon_ctx_remove(struct decon_context *ctx)`
`137`	`137`	`static u32 decon_calc_clkdiv(struct decon_context *ctx,`
`138`	`138`	`const struct drm_display_mode *mode)`
`139`	`139`	`{`
`140`		`- unsigned long ideal_clk = mode->clock;`
	`140`	`+ unsigned long ideal_clk = mode->clock * 1000;`
`141`	`141`	`u32 clkdiv;`
`142`	`142`
`143`	`143`	`/* Find the clock divider value that gets us closest to ideal_clk */`