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torvaldstorvalds
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Merge tag 'pinctrl-v6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij: "I'm mostly on vacation but what would vacation be without a few critical fixes so people can use their gaming laptops when hiding away from the sun (or rain)? - Fix a really annoying interrupt storm in the AMD driver affecting Asus TUF gaming notebooks - Fix device tree parsing in the Renesas driver" * tag 'pinctrl-v6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: amd: Unify debounce handling into amd_pinconf_set() pinctrl: amd: Drop pull up select configuration pinctrl: amd: Use amd_pinconf_set() for all config options pinctrl: amd: Only use special debounce behavior for GPIO 0 pinctrl: renesas: rzg2l: Handle non-unique subnode names pinctrl: renesas: rzv2m: Handle non-unique subnode names
2 parents fe756ad + 04e601f commit ede950b

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4 files changed

+63
-55
lines changed

4 files changed

+63
-55
lines changed

‎drivers/pinctrl/pinctrl-amd.c‎

Lines changed: 23 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -116,21 +116,19 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
116116
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
117117
}
118118

119-
static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
120-
unsigned debounce)
119+
static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset,
120+
unsigned int debounce)
121121
{
122122
u32 time;
123123
u32 pin_reg;
124124
int ret = 0;
125-
unsigned long flags;
126-
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
127-
128-
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
129125

130126
/* Use special handling for Pin0 debounce */
131-
pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
132-
if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
133-
debounce = 0;
127+
if (offset == 0) {
128+
pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
129+
if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
130+
debounce = 0;
131+
}
134132

135133
pin_reg = readl(gpio_dev->base + offset * 4);
136134

@@ -182,23 +180,10 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
182180
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
183181
}
184182
writel(pin_reg, gpio_dev->base + offset * 4);
185-
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
186183

187184
return ret;
188185
}
189186

190-
static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
191-
unsigned long config)
192-
{
193-
u32 debounce;
194-
195-
if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
196-
return -ENOTSUPP;
197-
198-
debounce = pinconf_to_config_argument(config);
199-
return amd_gpio_set_debounce(gc, offset, debounce);
200-
}
201-
202187
#ifdef CONFIG_DEBUG_FS
203188
static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
204189
{
@@ -220,7 +205,6 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
220205
char *pin_sts;
221206
char *interrupt_sts;
222207
char *wake_sts;
223-
char *pull_up_sel;
224208
char *orientation;
225209
char debounce_value[40];
226210
char *debounce_enable;
@@ -328,14 +312,9 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
328312
seq_printf(s, " %s|", wake_sts);
329313

330314
if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
331-
if (pin_reg & BIT(PULL_UP_SEL_OFF))
332-
pull_up_sel = "8k";
333-
else
334-
pull_up_sel = "4k";
335-
seq_printf(s, "%s ↑|",
336-
pull_up_sel);
315+
seq_puts(s, " ↑ |");
337316
} else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) {
338-
seq_puts(s, " ↓|");
317+
seq_puts(s, " ↓ |");
339318
} else {
340319
seq_puts(s, " |");
341320
}
@@ -761,7 +740,7 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev,
761740
break;
762741

763742
case PIN_CONFIG_BIAS_PULL_UP:
764-
arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
743+
arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0);
765744
break;
766745

767746
case PIN_CONFIG_DRIVE_STRENGTH:
@@ -780,7 +759,7 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev,
780759
}
781760

782761
static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
783-
unsigned long *configs, unsigned num_configs)
762+
unsigned long *configs, unsigned int num_configs)
784763
{
785764
int i;
786765
u32 arg;
@@ -798,20 +777,17 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
798777

799778
switch (param) {
800779
case PIN_CONFIG_INPUT_DEBOUNCE:
801-
pin_reg &= ~DB_TMR_OUT_MASK;
802-
pin_reg |= arg & DB_TMR_OUT_MASK;
803-
break;
780+
ret = amd_gpio_set_debounce(gpio_dev, pin, arg);
781+
goto out_unlock;
804782

805783
case PIN_CONFIG_BIAS_PULL_DOWN:
806784
pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
807785
pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
808786
break;
809787

810788
case PIN_CONFIG_BIAS_PULL_UP:
811-
pin_reg &= ~BIT(PULL_UP_SEL_OFF);
812-
pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
813789
pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
814-
pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
790+
pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF;
815791
break;
816792

817793
case PIN_CONFIG_DRIVE_STRENGTH:
@@ -829,6 +805,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
829805

830806
writel(pin_reg, gpio_dev->base + pin*4);
831807
}
808+
out_unlock:
832809
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
833810

834811
return ret;
@@ -870,6 +847,14 @@ static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
870847
return 0;
871848
}
872849

850+
static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin,
851+
unsigned long config)
852+
{
853+
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
854+
855+
return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
856+
}
857+
873858
static const struct pinconf_ops amd_pinconf_ops = {
874859
.pin_config_get = amd_pinconf_get,
875860
.pin_config_set = amd_pinconf_set,

‎drivers/pinctrl/pinctrl-amd.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,6 @@
3636
#define WAKE_CNTRL_OFF_S4 15
3737
#define PIN_STS_OFF 16
3838
#define DRV_STRENGTH_SEL_OFF 17
39-
#define PULL_UP_SEL_OFF 19
4039
#define PULL_UP_ENABLE_OFF 20
4140
#define PULL_DOWN_ENABLE_OFF 21
4241
#define OUTPUT_VALUE_OFF 22

‎drivers/pinctrl/renesas/pinctrl-rzg2l.c‎

Lines changed: 20 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -249,6 +249,7 @@ static int rzg2l_map_add_config(struct pinctrl_map *map,
249249

250250
static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
251251
struct device_node *np,
252+
struct device_node *parent,
252253
struct pinctrl_map **map,
253254
unsigned int *num_maps,
254255
unsigned int *index)
@@ -266,6 +267,7 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
266267
struct property *prop;
267268
int ret, gsel, fsel;
268269
const char **pin_fn;
270+
const char *name;
269271
const char *pin;
270272

271273
pinmux = of_find_property(np, "pinmux", NULL);
@@ -349,8 +351,19 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
349351
psel_val[i] = MUX_FUNC(value);
350352
}
351353

354+
if (parent) {
355+
name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
356+
parent, np);
357+
if (!name) {
358+
ret = -ENOMEM;
359+
goto done;
360+
}
361+
} else {
362+
name = np->name;
363+
}
364+
352365
/* Register a single pin group listing all the pins we read from DT */
353-
gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
366+
gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);
354367
if (gsel < 0) {
355368
ret = gsel;
356369
goto done;
@@ -360,17 +373,16 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
360373
* Register a single group function where the 'data' is an array PSEL
361374
* register values read from DT.
362375
*/
363-
pin_fn[0] = np->name;
364-
fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
365-
psel_val);
376+
pin_fn[0] = name;
377+
fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);
366378
if (fsel < 0) {
367379
ret = fsel;
368380
goto remove_group;
369381
}
370382

371383
maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
372-
maps[idx].data.mux.group = np->name;
373-
maps[idx].data.mux.function = np->name;
384+
maps[idx].data.mux.group = name;
385+
maps[idx].data.mux.function = name;
374386
idx++;
375387

376388
dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
@@ -417,7 +429,7 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
417429
index = 0;
418430

419431
for_each_child_of_node(np, child) {
420-
ret = rzg2l_dt_subnode_to_map(pctldev, child, map,
432+
ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map,
421433
num_maps, &index);
422434
if (ret < 0) {
423435
of_node_put(child);
@@ -426,7 +438,7 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
426438
}
427439

428440
if (*num_maps == 0) {
429-
ret = rzg2l_dt_subnode_to_map(pctldev, np, map,
441+
ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map,
430442
num_maps, &index);
431443
if (ret < 0)
432444
goto done;

‎drivers/pinctrl/renesas/pinctrl-rzv2m.c‎

Lines changed: 20 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -209,6 +209,7 @@ static int rzv2m_map_add_config(struct pinctrl_map *map,
209209

210210
static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev,
211211
struct device_node *np,
212+
struct device_node *parent,
212213
struct pinctrl_map **map,
213214
unsigned int *num_maps,
214215
unsigned int *index)
@@ -226,6 +227,7 @@ static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev,
226227
struct property *prop;
227228
int ret, gsel, fsel;
228229
const char **pin_fn;
230+
const char *name;
229231
const char *pin;
230232

231233
pinmux = of_find_property(np, "pinmux", NULL);
@@ -309,8 +311,19 @@ static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev,
309311
psel_val[i] = MUX_FUNC(value);
310312
}
311313

314+
if (parent) {
315+
name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
316+
parent, np);
317+
if (!name) {
318+
ret = -ENOMEM;
319+
goto done;
320+
}
321+
} else {
322+
name = np->name;
323+
}
324+
312325
/* Register a single pin group listing all the pins we read from DT */
313-
gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
326+
gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);
314327
if (gsel < 0) {
315328
ret = gsel;
316329
goto done;
@@ -320,17 +333,16 @@ static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev,
320333
* Register a single group function where the 'data' is an array PSEL
321334
* register values read from DT.
322335
*/
323-
pin_fn[0] = np->name;
324-
fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
325-
psel_val);
336+
pin_fn[0] = name;
337+
fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);
326338
if (fsel < 0) {
327339
ret = fsel;
328340
goto remove_group;
329341
}
330342

331343
maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
332-
maps[idx].data.mux.group = np->name;
333-
maps[idx].data.mux.function = np->name;
344+
maps[idx].data.mux.group = name;
345+
maps[idx].data.mux.function = name;
334346
idx++;
335347

336348
dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
@@ -377,7 +389,7 @@ static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev,
377389
index = 0;
378390

379391
for_each_child_of_node(np, child) {
380-
ret = rzv2m_dt_subnode_to_map(pctldev, child, map,
392+
ret = rzv2m_dt_subnode_to_map(pctldev, child, np, map,
381393
num_maps, &index);
382394
if (ret < 0) {
383395
of_node_put(child);
@@ -386,7 +398,7 @@ static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev,
386398
}
387399

388400
if (*num_maps == 0) {
389-
ret = rzv2m_dt_subnode_to_map(pctldev, np, map,
401+
ret = rzv2m_dt_subnode_to_map(pctldev, np, NULL, map,
390402
num_maps, &index);
391403
if (ret < 0)
392404
goto done;

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