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Shyam Sundar S Kij-intel
Shyam Sundar S K
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ij-intel
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platform/x86/amd/pmc: Move macros and structures to the PMC header file
To improve the code organization and readability, move the macros and structures from the AMD PMC driver to the PMC header file. Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com> Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Link: https://lore.kernel.org/r/20250305142615.410178-2-Shyam-sundar.S-k@amd.com Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
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‎drivers/platform/x86/amd/pmc/pmc.c‎

Lines changed: 0 additions & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -32,70 +32,6 @@
3232

3333
#include "pmc.h"
3434

35-
/* SMU communication registers */
36-
#define AMD_PMC_REGISTER_RESPONSE 0x980
37-
#define AMD_PMC_REGISTER_ARGUMENT 0x9BC
38-
39-
/* PMC Scratch Registers */
40-
#define AMD_PMC_SCRATCH_REG_CZN 0x94
41-
#define AMD_PMC_SCRATCH_REG_YC 0xD14
42-
#define AMD_PMC_SCRATCH_REG_1AH 0xF14
43-
44-
/* STB Registers */
45-
#define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001
46-
#define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
47-
#define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003
48-
49-
/* Base address of SMU for mapping physical address to virtual address */
50-
#define AMD_PMC_MAPPING_SIZE 0x01000
51-
#define AMD_PMC_BASE_ADDR_OFFSET 0x10000
52-
#define AMD_PMC_BASE_ADDR_LO 0x13B102E8
53-
#define AMD_PMC_BASE_ADDR_HI 0x13B102EC
54-
#define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
55-
#define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
56-
57-
/* SMU Response Codes */
58-
#define AMD_PMC_RESULT_OK 0x01
59-
#define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
60-
#define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
61-
#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
62-
#define AMD_PMC_RESULT_FAILED 0xFF
63-
64-
/* FCH SSC Registers */
65-
#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
66-
#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
67-
#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
68-
#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
69-
#define FCH_SSC_MAPPING_SIZE 0x800
70-
#define FCH_BASE_PHY_ADDR_LOW 0xFED81100
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#define FCH_BASE_PHY_ADDR_HIGH 0x00000000
72-
73-
/* SMU Message Definations */
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#define SMU_MSG_GETSMUVERSION 0x02
75-
#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
76-
#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
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#define SMU_MSG_LOG_START 0x06
78-
#define SMU_MSG_LOG_RESET 0x07
79-
#define SMU_MSG_LOG_DUMP_DATA 0x08
80-
#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
81-
82-
#define PMC_MSG_DELAY_MIN_US 50
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#define RESPONSE_REGISTER_LOOP_MAX 20000
84-
85-
#define DELAY_MIN_US 2000
86-
#define DELAY_MAX_US 3000
87-
88-
enum amd_pmc_def {
89-
MSG_TEST = 0x01,
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MSG_OS_HINT_PCO,
91-
MSG_OS_HINT_RN,
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};
93-
94-
struct amd_pmc_bit_map {
95-
const char *name;
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u32 bit_mask;
97-
};
98-
9935
static const struct amd_pmc_bit_map soc15_ip_blk_v2[] = {
10036
{"DISPLAY", BIT(0)},
10137
{"CPU", BIT(1)},
@@ -165,23 +101,6 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3
165101
iowrite32(val, dev->regbase + reg_offset);
166102
}
167103

168-
struct smu_metrics {
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u32 table_version;
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u32 hint_count;
171-
u32 s0i3_last_entry_status;
172-
u32 timein_s0i2;
173-
u64 timeentering_s0i3_lastcapture;
174-
u64 timeentering_s0i3_totaltime;
175-
u64 timeto_resume_to_os_lastcapture;
176-
u64 timeto_resume_to_os_totaltime;
177-
u64 timein_s0i3_lastcapture;
178-
u64 timein_s0i3_totaltime;
179-
u64 timein_swdrips_lastcapture;
180-
u64 timein_swdrips_totaltime;
181-
u64 timecondition_notmet_lastcapture[32];
182-
u64 timecondition_notmet_totaltime[32];
183-
} __packed;
184-
185104
static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
186105
{
187106
switch (dev->cpu_id) {

‎drivers/platform/x86/amd/pmc/pmc.h‎

Lines changed: 81 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,59 @@
1414
#include <linux/types.h>
1515
#include <linux/mutex.h>
1616

17+
/* SMU communication registers */
18+
#define AMD_PMC_REGISTER_RESPONSE 0x980
19+
#define AMD_PMC_REGISTER_ARGUMENT 0x9BC
20+
21+
/* PMC Scratch Registers */
22+
#define AMD_PMC_SCRATCH_REG_CZN 0x94
23+
#define AMD_PMC_SCRATCH_REG_YC 0xD14
24+
#define AMD_PMC_SCRATCH_REG_1AH 0xF14
25+
26+
/* STB Registers */
27+
#define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001
28+
#define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
29+
#define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003
30+
31+
/* Base address of SMU for mapping physical address to virtual address */
32+
#define AMD_PMC_MAPPING_SIZE 0x01000
33+
#define AMD_PMC_BASE_ADDR_OFFSET 0x10000
34+
#define AMD_PMC_BASE_ADDR_LO 0x13B102E8
35+
#define AMD_PMC_BASE_ADDR_HI 0x13B102EC
36+
#define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
37+
#define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
38+
39+
/* SMU Response Codes */
40+
#define AMD_PMC_RESULT_OK 0x01
41+
#define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
42+
#define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
43+
#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
44+
#define AMD_PMC_RESULT_FAILED 0xFF
45+
46+
/* FCH SSC Registers */
47+
#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
48+
#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
49+
#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
50+
#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
51+
#define FCH_SSC_MAPPING_SIZE 0x800
52+
#define FCH_BASE_PHY_ADDR_LOW 0xFED81100
53+
#define FCH_BASE_PHY_ADDR_HIGH 0x00000000
54+
55+
/* SMU Message Definations */
56+
#define SMU_MSG_GETSMUVERSION 0x02
57+
#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
58+
#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
59+
#define SMU_MSG_LOG_START 0x06
60+
#define SMU_MSG_LOG_RESET 0x07
61+
#define SMU_MSG_LOG_DUMP_DATA 0x08
62+
#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
63+
64+
#define PMC_MSG_DELAY_MIN_US 50
65+
#define RESPONSE_REGISTER_LOOP_MAX 20000
66+
67+
#define DELAY_MIN_US 2000
68+
#define DELAY_MAX_US 3000
69+
1770
enum s2d_msg_port {
1871
MSG_PORT_PMC,
1972
MSG_PORT_S2D,
@@ -65,6 +118,34 @@ struct amd_pmc_dev {
65118
struct stb_arg stb_arg;
66119
};
67120

121+
struct amd_pmc_bit_map {
122+
const char *name;
123+
u32 bit_mask;
124+
};
125+
126+
struct smu_metrics {
127+
u32 table_version;
128+
u32 hint_count;
129+
u32 s0i3_last_entry_status;
130+
u32 timein_s0i2;
131+
u64 timeentering_s0i3_lastcapture;
132+
u64 timeentering_s0i3_totaltime;
133+
u64 timeto_resume_to_os_lastcapture;
134+
u64 timeto_resume_to_os_totaltime;
135+
u64 timein_s0i3_lastcapture;
136+
u64 timein_s0i3_totaltime;
137+
u64 timein_swdrips_lastcapture;
138+
u64 timein_swdrips_totaltime;
139+
u64 timecondition_notmet_lastcapture[32];
140+
u64 timecondition_notmet_totaltime[32];
141+
} __packed;
142+
143+
enum amd_pmc_def {
144+
MSG_TEST = 0x01,
145+
MSG_OS_HINT_PCO,
146+
MSG_OS_HINT_RN,
147+
};
148+
68149
void amd_pmc_process_restore_quirks(struct amd_pmc_dev *dev);
69150
void amd_pmc_quirks_init(struct amd_pmc_dev *dev);
70151
void amd_mp2_stb_init(struct amd_pmc_dev *dev);

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