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174 | 174 | #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 |
175 | 175 | #define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 |
176 | 176 | #define SIERRA_DEQ_TAU_CTRL3_PREG 0x152 |
177 | | -#define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x158 |
| 177 | +#define SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG 0x158 |
178 | 178 | #define SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG 0x159 |
| 179 | +#define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x15C |
179 | 180 | #define SIERRA_DEQ_PICTRL_PREG 0x161 |
180 | 181 | #define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 |
181 | 182 | #define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 |
@@ -1733,7 +1734,7 @@ static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = { |
1733 | 1734 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
1734 | 1735 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
1735 | 1736 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
1736 | | - {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 1737 | + {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, |
1737 | 1738 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
1738 | 1739 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
1739 | 1740 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
@@ -1797,7 +1798,7 @@ static const struct cdns_reg_pairs ti_ml_pcie_100_no_ssc_ln_regs[] = { |
1797 | 1798 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
1798 | 1799 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
1799 | 1800 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
1800 | | - {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 1801 | + {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, |
1801 | 1802 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
1802 | 1803 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
1803 | 1804 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
@@ -1874,7 +1875,7 @@ static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = { |
1874 | 1875 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
1875 | 1876 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
1876 | 1877 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
1877 | | - {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 1878 | + {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, |
1878 | 1879 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
1879 | 1880 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
1880 | 1881 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
@@ -1941,7 +1942,7 @@ static const struct cdns_reg_pairs ti_ml_pcie_100_int_ssc_ln_regs[] = { |
1941 | 1942 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
1942 | 1943 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
1943 | 1944 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
1944 | | - {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 1945 | + {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, |
1945 | 1946 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
1946 | 1947 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
1947 | 1948 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
@@ -2012,7 +2013,7 @@ static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = { |
2012 | 2013 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
2013 | 2014 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
2014 | 2015 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
2015 | | - {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 2016 | + {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, |
2016 | 2017 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
2017 | 2018 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
2018 | 2019 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
@@ -2079,7 +2080,7 @@ static const struct cdns_reg_pairs ti_ml_pcie_100_ext_ssc_ln_regs[] = { |
2079 | 2080 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
2080 | 2081 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
2081 | 2082 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
2082 | | - {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 2083 | + {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, |
2083 | 2084 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
2084 | 2085 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
2085 | 2086 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
@@ -2140,7 +2141,7 @@ static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = { |
2140 | 2141 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
2141 | 2142 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
2142 | 2143 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
2143 | | - {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 2144 | + {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, |
2144 | 2145 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
2145 | 2146 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
2146 | 2147 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
@@ -2215,7 +2216,7 @@ static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = { |
2215 | 2216 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
2216 | 2217 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
2217 | 2218 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
2218 | | - {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 2219 | + {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, |
2219 | 2220 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
2220 | 2221 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
2221 | 2222 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
@@ -2284,7 +2285,7 @@ static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { |
2284 | 2285 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
2285 | 2286 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
2286 | 2287 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
2287 | | - {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
| 2288 | + {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, |
2288 | 2289 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
2289 | 2290 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
2290 | 2291 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
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