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airliedairlied
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Merge tag 'drm-intel-gt-next-2025-03-12' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
UAPI Changes: - Increase I915_PARAM_MMAP_GTT_VERSION version to indicate support for partial mmaps (José Roberto de Souza) Driver Changes: Fixes/improvements/new stuff: - Implement vmap/vunmap GEM object functions (Asbjørn Sloth Tønnesen) Miscellaneous: - Various register definition cleanups (Ville Syrjälä) - Fix typo in a comment [gt/uc] (Yuichiro Tsuji) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Tvrtko Ursulin <tursulin@igalia.com> Link: https://patchwork.freedesktop.org/patch/msgid/Z9IXs5CzHHKScuQn@linux
2 parents a82866f + bfef148 commit cf05922

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9 files changed

+165
-174
lines changed

9 files changed

+165
-174
lines changed

‎drivers/gpu/drm/i915/gem/i915_gem_mman.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -164,6 +164,9 @@ static unsigned int tile_row_pages(const struct drm_i915_gem_object *obj)
164164
* 4 - Support multiple fault handlers per object depending on object's
165165
* backing storage (a.k.a. MMAP_OFFSET).
166166
*
167+
* 5 - Support multiple partial mmaps(mmap part of BO + unmap a offset, multiple
168+
* times with different size and offset).
169+
*
167170
* Restrictions:
168171
*
169172
* * snoopable objects cannot be accessed via the GTT. It can cause machine
@@ -191,7 +194,7 @@ static unsigned int tile_row_pages(const struct drm_i915_gem_object *obj)
191194
*/
192195
int i915_gem_mmap_gtt_version(void)
193196
{
194-
return 4;
197+
return 5;
195198
}
196199

197200
static inline struct i915_gtt_view

‎drivers/gpu/drm/i915/gem/i915_gem_object.c‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -873,6 +873,30 @@ bool i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj)
873873
return lmem_placement;
874874
}
875875

876+
static int i915_gem_vmap_object(struct drm_gem_object *gem_obj,
877+
struct iosys_map *map)
878+
{
879+
struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
880+
void *vaddr;
881+
882+
vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
883+
if (IS_ERR(vaddr))
884+
return PTR_ERR(vaddr);
885+
886+
iosys_map_set_vaddr(map, vaddr);
887+
888+
return 0;
889+
}
890+
891+
static void i915_gem_vunmap_object(struct drm_gem_object *gem_obj,
892+
struct iosys_map *map)
893+
{
894+
struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
895+
896+
i915_gem_object_flush_map(obj);
897+
i915_gem_object_unpin_map(obj);
898+
}
899+
876900
void i915_gem_init__objects(struct drm_i915_private *i915)
877901
{
878902
INIT_WORK(&i915->mm.free_work, __i915_gem_free_work);
@@ -896,6 +920,8 @@ static const struct drm_gem_object_funcs i915_gem_object_funcs = {
896920
.free = i915_gem_free_object,
897921
.close = i915_gem_close_object,
898922
.export = i915_gem_prime_export,
923+
.vmap = i915_gem_vmap_object,
924+
.vunmap = i915_gem_vunmap_object,
899925
};
900926

901927
/**

‎drivers/gpu/drm/i915/gt/intel_engine_cs.c‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -769,9 +769,8 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt)
769769
if (MEDIA_VER_FULL(i915) < IP_VER(12, 55))
770770
media_fuse = ~media_fuse;
771771

772-
vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
773-
vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
774-
GEN11_GT_VEBOX_DISABLE_SHIFT;
772+
vdbox_mask = REG_FIELD_GET(GEN11_GT_VDBOX_DISABLE_MASK, media_fuse);
773+
vebox_mask = REG_FIELD_GET(GEN11_GT_VEBOX_DISABLE_MASK, media_fuse);
775774

776775
if (MEDIA_VER_FULL(i915) >= IP_VER(12, 55)) {
777776
fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);

‎drivers/gpu/drm/i915/gt/intel_gt.c‎

Lines changed: 38 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -302,25 +302,48 @@ static void gen6_check_faults(struct intel_gt *gt)
302302
{
303303
struct intel_engine_cs *engine;
304304
enum intel_engine_id id;
305-
unsigned long fault;
306305

307306
for_each_engine(engine, gt, id) {
307+
u32 fault;
308+
308309
fault = GEN6_RING_FAULT_REG_READ(engine);
310+
309311
if (fault & RING_FAULT_VALID) {
310312
gt_dbg(gt, "Unexpected fault\n"
311-
"\tAddr: 0x%08lx\n"
313+
"\tAddr: 0x%08x\n"
312314
"\tAddress space: %s\n"
313-
"\tSource ID: %ld\n"
314-
"\tType: %ld\n",
315-
fault & PAGE_MASK,
315+
"\tSource ID: %d\n"
316+
"\tType: %d\n",
317+
fault & RING_FAULT_VADDR_MASK,
316318
fault & RING_FAULT_GTTSEL_MASK ?
317319
"GGTT" : "PPGTT",
318-
RING_FAULT_SRCID(fault),
319-
RING_FAULT_FAULT_TYPE(fault));
320+
REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),
321+
REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));
320322
}
321323
}
322324
}
323325

326+
static void gen8_report_fault(struct intel_gt *gt, u32 fault,
327+
u32 fault_data0, u32 fault_data1)
328+
{
329+
u64 fault_addr;
330+
331+
fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
332+
((u64)fault_data0 << 12);
333+
334+
gt_dbg(gt, "Unexpected fault\n"
335+
"\tAddr: 0x%08x_%08x\n"
336+
"\tAddress space: %s\n"
337+
"\tEngine ID: %d\n"
338+
"\tSource ID: %d\n"
339+
"\tType: %d\n",
340+
upper_32_bits(fault_addr), lower_32_bits(fault_addr),
341+
fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
342+
REG_FIELD_GET(RING_FAULT_ENGINE_ID_MASK, fault),
343+
REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),
344+
REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));
345+
}
346+
324347
static void xehp_check_faults(struct intel_gt *gt)
325348
{
326349
u32 fault;
@@ -333,28 +356,10 @@ static void xehp_check_faults(struct intel_gt *gt)
333356
* toward the primary instance.
334357
*/
335358
fault = intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
336-
if (fault & RING_FAULT_VALID) {
337-
u32 fault_data0, fault_data1;
338-
u64 fault_addr;
339-
340-
fault_data0 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0);
341-
fault_data1 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1);
342-
343-
fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
344-
((u64)fault_data0 << 12);
345-
346-
gt_dbg(gt, "Unexpected fault\n"
347-
"\tAddr: 0x%08x_%08x\n"
348-
"\tAddress space: %s\n"
349-
"\tEngine ID: %d\n"
350-
"\tSource ID: %d\n"
351-
"\tType: %d\n",
352-
upper_32_bits(fault_addr), lower_32_bits(fault_addr),
353-
fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
354-
GEN8_RING_FAULT_ENGINE_ID(fault),
355-
RING_FAULT_SRCID(fault),
356-
RING_FAULT_FAULT_TYPE(fault));
357-
}
359+
if (fault & RING_FAULT_VALID)
360+
gen8_report_fault(gt, fault,
361+
intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0),
362+
intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1));
358363
}
359364

360365
static void gen8_check_faults(struct intel_gt *gt)
@@ -374,28 +379,10 @@ static void gen8_check_faults(struct intel_gt *gt)
374379
}
375380

376381
fault = intel_uncore_read(uncore, fault_reg);
377-
if (fault & RING_FAULT_VALID) {
378-
u32 fault_data0, fault_data1;
379-
u64 fault_addr;
380-
381-
fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
382-
fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
383-
384-
fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
385-
((u64)fault_data0 << 12);
386-
387-
gt_dbg(gt, "Unexpected fault\n"
388-
"\tAddr: 0x%08x_%08x\n"
389-
"\tAddress space: %s\n"
390-
"\tEngine ID: %d\n"
391-
"\tSource ID: %d\n"
392-
"\tType: %d\n",
393-
upper_32_bits(fault_addr), lower_32_bits(fault_addr),
394-
fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
395-
GEN8_RING_FAULT_ENGINE_ID(fault),
396-
RING_FAULT_SRCID(fault),
397-
RING_FAULT_FAULT_TYPE(fault));
398-
}
382+
if (fault & RING_FAULT_VALID)
383+
gen8_report_fault(gt, fault,
384+
intel_uncore_read(uncore, fault_data0_reg),
385+
intel_uncore_read(uncore, fault_data1_reg));
399386
}
400387

401388
void intel_gt_check_and_clear_faults(struct intel_gt *gt)

‎drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c‎

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -35,9 +35,7 @@ static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore,
3535
u32 f24_mhz = 24000000;
3636
u32 f25_mhz = 25000000;
3737
u32 f38_4_mhz = 38400000;
38-
u32 crystal_clock =
39-
(rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
40-
GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
38+
u32 crystal_clock = rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK;
4139

4240
switch (crystal_clock) {
4341
case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
@@ -80,8 +78,7 @@ static u32 gen11_read_clock_frequency(struct intel_uncore *uncore)
8078
* register increments from this frequency (it might
8179
* increment only every few clock cycle).
8280
*/
83-
freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
84-
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
81+
freq >>= 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0);
8582
}
8683

8784
return freq;
@@ -102,8 +99,7 @@ static u32 gen9_read_clock_frequency(struct intel_uncore *uncore)
10299
* register increments from this frequency (it might
103100
* increment only every few clock cycle).
104101
*/
105-
freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
106-
CTC_SHIFT_PARAMETER_SHIFT);
102+
freq >>= 3 - REG_FIELD_GET(CTC_SHIFT_PARAMETER_MASK, ctc_reg);
107103
}
108104

109105
return freq;

‎drivers/gpu/drm/i915/gt/intel_gt_mcr.c‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -121,9 +121,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
121121
gt->info.mslice_mask =
122122
intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
123123
GEN_DSS_PER_MSLICE);
124-
gt->info.mslice_mask |=
125-
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
126-
GEN12_MEML3_EN_MASK);
124+
gt->info.mslice_mask |= REG_FIELD_GET(GEN12_MEML3_EN_MASK,
125+
intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3));
127126

128127
if (!gt->info.mslice_mask) /* should be impossible! */
129128
gt_warn(gt, "mslice mask all zero!\n");

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