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clk: meson: mpll: Delete a useless spinlock from the MPLL
The register corresponding to MPLL does not share the same register with other module drivers, so there is no concurrent access to the register with other modules drivers. The spinlock defined in struct meson_clk_mpll_data is no longer useful. Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20240925-mpll_spinlock-v2-1-8f9b73588ec1@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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-39
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‎drivers/clk/meson/axg.c‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -23,8 +23,6 @@
2323

2424
#include <dt-bindings/clock/axg-clkc.h>
2525

26-
static DEFINE_SPINLOCK(meson_clk_lock);
27-
2826
static struct clk_regmap axg_fixed_pll_dco = {
2927
.data = &(struct meson_clk_pll_data){
3028
.en = {
@@ -506,7 +504,6 @@ static struct clk_regmap axg_mpll0_div = {
506504
.shift = 0,
507505
.width = 1,
508506
},
509-
.lock = &meson_clk_lock,
510507
.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
511508
},
512509
.hw.init = &(struct clk_init_data){
@@ -557,7 +554,6 @@ static struct clk_regmap axg_mpll1_div = {
557554
.shift = 1,
558555
.width = 1,
559556
},
560-
.lock = &meson_clk_lock,
561557
.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
562558
},
563559
.hw.init = &(struct clk_init_data){
@@ -613,7 +609,6 @@ static struct clk_regmap axg_mpll2_div = {
613609
.shift = 2,
614610
.width = 1,
615611
},
616-
.lock = &meson_clk_lock,
617612
.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
618613
},
619614
.hw.init = &(struct clk_init_data){
@@ -664,7 +659,6 @@ static struct clk_regmap axg_mpll3_div = {
664659
.shift = 3,
665660
.width = 1,
666661
},
667-
.lock = &meson_clk_lock,
668662
.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
669663
},
670664
.hw.init = &(struct clk_init_data){

‎drivers/clk/meson/clk-mpll.c‎

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -112,26 +112,15 @@ static int mpll_set_rate(struct clk_hw *hw,
112112
struct clk_regmap *clk = to_clk_regmap(hw);
113113
struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
114114
unsigned int sdm, n2;
115-
unsigned long flags = 0;
116115

117116
params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags);
118117

119-
if (mpll->lock)
120-
spin_lock_irqsave(mpll->lock, flags);
121-
else
122-
__acquire(mpll->lock);
123-
124118
/* Set the fractional part */
125119
meson_parm_write(clk->map, &mpll->sdm, sdm);
126120

127121
/* Set the integer divider part */
128122
meson_parm_write(clk->map, &mpll->n2, n2);
129123

130-
if (mpll->lock)
131-
spin_unlock_irqrestore(mpll->lock, flags);
132-
else
133-
__release(mpll->lock);
134-
135124
return 0;
136125
}
137126

‎drivers/clk/meson/clk-mpll.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,6 @@ struct meson_clk_mpll_data {
2020
struct parm misc;
2121
const struct reg_sequence *init_regs;
2222
unsigned int init_count;
23-
spinlock_t *lock;
2423
u8 flags;
2524
};
2625

‎drivers/clk/meson/g12a.c‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,6 @@
2828

2929
#include <dt-bindings/clock/g12a-clkc.h>
3030

31-
static DEFINE_SPINLOCK(meson_clk_lock);
32-
3331
static struct clk_regmap g12a_fixed_pll_dco = {
3432
.data = &(struct meson_clk_pll_data){
3533
.en = {
@@ -2225,7 +2223,6 @@ static struct clk_regmap g12a_mpll0_div = {
22252223
.shift = 29,
22262224
.width = 1,
22272225
},
2228-
.lock = &meson_clk_lock,
22292226
.init_regs = g12a_mpll0_init_regs,
22302227
.init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
22312228
},
@@ -2279,7 +2276,6 @@ static struct clk_regmap g12a_mpll1_div = {
22792276
.shift = 29,
22802277
.width = 1,
22812278
},
2282-
.lock = &meson_clk_lock,
22832279
.init_regs = g12a_mpll1_init_regs,
22842280
.init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
22852281
},
@@ -2333,7 +2329,6 @@ static struct clk_regmap g12a_mpll2_div = {
23332329
.shift = 29,
23342330
.width = 1,
23352331
},
2336-
.lock = &meson_clk_lock,
23372332
.init_regs = g12a_mpll2_init_regs,
23382333
.init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
23392334
},
@@ -2387,7 +2382,6 @@ static struct clk_regmap g12a_mpll3_div = {
23872382
.shift = 29,
23882383
.width = 1,
23892384
},
2390-
.lock = &meson_clk_lock,
23912385
.init_regs = g12a_mpll3_init_regs,
23922386
.init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
23932387
},

‎drivers/clk/meson/gxbb.c‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,6 @@
1919

2020
#include <dt-bindings/clock/gxbb-clkc.h>
2121

22-
static DEFINE_SPINLOCK(meson_clk_lock);
23-
2422
static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
2523
PLL_PARAMS(32, 1),
2624
PLL_PARAMS(33, 1),
@@ -731,7 +729,6 @@ static struct clk_regmap gxbb_mpll0_div = {
731729
.shift = 16,
732730
.width = 9,
733731
},
734-
.lock = &meson_clk_lock,
735732
},
736733
.hw.init = &(struct clk_init_data){
737734
.name = "mpll0_div",
@@ -760,7 +757,6 @@ static struct clk_regmap gxl_mpll0_div = {
760757
.shift = 16,
761758
.width = 9,
762759
},
763-
.lock = &meson_clk_lock,
764760
},
765761
.hw.init = &(struct clk_init_data){
766762
.name = "mpll0_div",
@@ -812,7 +808,6 @@ static struct clk_regmap gxbb_mpll1_div = {
812808
.shift = 16,
813809
.width = 9,
814810
},
815-
.lock = &meson_clk_lock,
816811
},
817812
.hw.init = &(struct clk_init_data){
818813
.name = "mpll1_div",
@@ -855,7 +850,6 @@ static struct clk_regmap gxbb_mpll2_div = {
855850
.shift = 16,
856851
.width = 9,
857852
},
858-
.lock = &meson_clk_lock,
859853
},
860854
.hw.init = &(struct clk_init_data){
861855
.name = "mpll2_div",

‎drivers/clk/meson/meson8b.c‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -492,7 +492,6 @@ static struct clk_regmap meson8b_mpll0_div = {
492492
.shift = 25,
493493
.width = 1,
494494
},
495-
.lock = &meson_clk_lock,
496495
},
497496
.hw.init = &(struct clk_init_data){
498497
.name = "mpll0_div",
@@ -537,7 +536,6 @@ static struct clk_regmap meson8b_mpll1_div = {
537536
.shift = 16,
538537
.width = 9,
539538
},
540-
.lock = &meson_clk_lock,
541539
},
542540
.hw.init = &(struct clk_init_data){
543541
.name = "mpll1_div",
@@ -582,7 +580,6 @@ static struct clk_regmap meson8b_mpll2_div = {
582580
.shift = 16,
583581
.width = 9,
584582
},
585-
.lock = &meson_clk_lock,
586583
},
587584
.hw.init = &(struct clk_init_data){
588585
.name = "mpll2_div",

‎drivers/clk/meson/s4-pll.c‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,6 @@
1717
#include "meson-clkc-utils.h"
1818
#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
1919

20-
static DEFINE_SPINLOCK(meson_clk_lock);
21-
2220
/*
2321
* These clock are a fixed value (fixed_pll is 2GHz) that is initialized by ROMcode.
2422
* The chip was changed fixed pll for security reasons. Fixed PLL registers are not writable
@@ -547,7 +545,6 @@ static struct clk_regmap s4_mpll0_div = {
547545
.shift = 29,
548546
.width = 1,
549547
},
550-
.lock = &meson_clk_lock,
551548
.init_regs = s4_mpll0_init_regs,
552549
.init_count = ARRAY_SIZE(s4_mpll0_init_regs),
553550
},
@@ -601,7 +598,6 @@ static struct clk_regmap s4_mpll1_div = {
601598
.shift = 29,
602599
.width = 1,
603600
},
604-
.lock = &meson_clk_lock,
605601
.init_regs = s4_mpll1_init_regs,
606602
.init_count = ARRAY_SIZE(s4_mpll1_init_regs),
607603
},
@@ -655,7 +651,6 @@ static struct clk_regmap s4_mpll2_div = {
655651
.shift = 29,
656652
.width = 1,
657653
},
658-
.lock = &meson_clk_lock,
659654
.init_regs = s4_mpll2_init_regs,
660655
.init_count = ARRAY_SIZE(s4_mpll2_init_regs),
661656
},
@@ -709,7 +704,6 @@ static struct clk_regmap s4_mpll3_div = {
709704
.shift = 29,
710705
.width = 1,
711706
},
712-
.lock = &meson_clk_lock,
713707
.init_regs = s4_mpll3_init_regs,
714708
.init_count = ARRAY_SIZE(s4_mpll3_init_regs),
715709
},

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