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Merge tag 'v6.4-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
Fixes for the reset pin on nanopi r5c, a reset line on SOQuartz, a duplicate usb regulator on rock64 and PCIe register mappings on rk356x. Also some missing cache properties. * tag 'v6.4-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: Fix rk356x PCIe register and range mappings arm64: dts: rockchip: fix button reset pin for nanopi r5c arm64: dts: rockchip: fix nEXTRST on SOQuartz arm64: dts: rockchip: add missing cache properties arm64: dts: rockchip: fix USB regulator on ROCK64 Link: https://lore.kernel.org/r/2885657.e9J7NaK4W3@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents 858fd16 + 568a67e commit 5b017b5

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+50
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‎arch/arm64/boot/dts/rockchip/rk3308.dtsi‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,7 @@
9797
l2: l2-cache {
9898
compatible = "cache";
9999
cache-level = <2>;
100+
cache-unified;
100101
};
101102
};
102103

‎arch/arm64/boot/dts/rockchip/rk3328-rock64.dts‎

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,8 @@
3737
vin-supply = <&vcc_io>;
3838
};
3939

40-
vcc_host_5v: vcc-host-5v-regulator {
40+
/* Common enable line for all of the rails mentioned in the labels */
41+
vcc_host_5v: vcc_host1_5v: vcc_otg_5v: vcc-host-5v-regulator {
4142
compatible = "regulator-fixed";
4243
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
4344
pinctrl-names = "default";
@@ -48,17 +49,6 @@
4849
vin-supply = <&vcc_sys>;
4950
};
5051

51-
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
52-
compatible = "regulator-fixed";
53-
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
54-
pinctrl-names = "default";
55-
pinctrl-0 = <&usb20_host_drv>;
56-
regulator-name = "vcc_host1_5v";
57-
regulator-always-on;
58-
regulator-boot-on;
59-
vin-supply = <&vcc_sys>;
60-
};
61-
6252
vcc_sys: vcc-sys {
6353
compatible = "regulator-fixed";
6454
regulator-name = "vcc_sys";

‎arch/arm64/boot/dts/rockchip/rk3328.dtsi‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,7 @@
103103
l2: l2-cache0 {
104104
compatible = "cache";
105105
cache-level = <2>;
106+
cache-unified;
106107
};
107108
};
108109

‎arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts‎

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,16 @@
2828
regulator-max-microvolt = <5000000>;
2929
vin-supply = <&vcc12v_dcin>;
3030
};
31+
32+
vcc_sd_pwr: vcc-sd-pwr-regulator {
33+
compatible = "regulator-fixed";
34+
regulator-name = "vcc_sd_pwr";
35+
regulator-always-on;
36+
regulator-boot-on;
37+
regulator-min-microvolt = <3300000>;
38+
regulator-max-microvolt = <3300000>;
39+
vin-supply = <&vcc3v3_sys>;
40+
};
3141
};
3242

3343
/* phy for pcie */
@@ -130,13 +140,7 @@
130140
};
131141

132142
&sdmmc0 {
133-
vmmc-supply = <&sdmmc_pwr>;
134-
status = "okay";
135-
};
136-
137-
&sdmmc_pwr {
138-
regulator-min-microvolt = <3300000>;
139-
regulator-max-microvolt = <3300000>;
143+
vmmc-supply = <&vcc_sd_pwr>;
140144
status = "okay";
141145
};
142146

‎arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi‎

Lines changed: 13 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -104,16 +104,6 @@
104104
regulator-max-microvolt = <3300000>;
105105
vin-supply = <&vcc5v0_sys>;
106106
};
107-
108-
sdmmc_pwr: sdmmc-pwr-regulator {
109-
compatible = "regulator-fixed";
110-
enable-active-high;
111-
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
112-
pinctrl-names = "default";
113-
pinctrl-0 = <&sdmmc_pwr_h>;
114-
regulator-name = "sdmmc_pwr";
115-
status = "disabled";
116-
};
117107
};
118108

119109
&cpu0 {
@@ -155,6 +145,19 @@
155145
status = "disabled";
156146
};
157147

148+
&gpio0 {
149+
nextrst-hog {
150+
gpio-hog;
151+
/*
152+
* GPIO_ACTIVE_LOW + output-low here means that the pin is set
153+
* to high, because output-low decides the value pre-inversion.
154+
*/
155+
gpios = <RK_PA5 GPIO_ACTIVE_LOW>;
156+
line-name = "nEXTRST";
157+
output-low;
158+
};
159+
};
160+
158161
&gpu {
159162
mali-supply = <&vdd_gpu>;
160163
status = "okay";
@@ -538,12 +541,6 @@
538541
rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
539542
};
540543
};
541-
542-
sdmmc-pwr {
543-
sdmmc_pwr_h: sdmmc-pwr-h {
544-
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
545-
};
546-
};
547544
};
548545

549546
&pmu_io_domains {

‎arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@
106106

107107
rockchip-key {
108108
reset_button_pin: reset-button-pin {
109-
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
109+
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
110110
};
111111
};
112112
};

‎arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -134,4 +134,3 @@
134134
};
135135
};
136136
};
137-

‎arch/arm64/boot/dts/rockchip/rk3568.dtsi‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -94,9 +94,10 @@
9494
power-domains = <&power RK3568_PD_PIPE>;
9595
reg = <0x3 0xc0400000 0x0 0x00400000>,
9696
<0x0 0xfe270000 0x0 0x00010000>,
97-
<0x3 0x7f000000 0x0 0x01000000>;
98-
ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
99-
<0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
97+
<0x0 0xf2000000 0x0 0x00100000>;
98+
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
99+
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
100+
<0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
100101
reg-names = "dbi", "apb", "config";
101102
resets = <&cru SRST_PCIE30X1_POWERUP>;
102103
reset-names = "pipe";
@@ -146,9 +147,10 @@
146147
power-domains = <&power RK3568_PD_PIPE>;
147148
reg = <0x3 0xc0800000 0x0 0x00400000>,
148149
<0x0 0xfe280000 0x0 0x00010000>,
149-
<0x3 0xbf000000 0x0 0x01000000>;
150-
ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
151-
<0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
150+
<0x0 0xf0000000 0x0 0x00100000>;
151+
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
152+
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
153+
<0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
152154
reg-names = "dbi", "apb", "config";
153155
resets = <&cru SRST_PCIE30X2_POWERUP>;
154156
reset-names = "pipe";

‎arch/arm64/boot/dts/rockchip/rk356x.dtsi‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -952,7 +952,7 @@
952952
compatible = "rockchip,rk3568-pcie";
953953
reg = <0x3 0xc0000000 0x0 0x00400000>,
954954
<0x0 0xfe260000 0x0 0x00010000>,
955-
<0x3 0x3f000000 0x0 0x01000000>;
955+
<0x0 0xf4000000 0x0 0x00100000>;
956956
reg-names = "dbi", "apb", "config";
957957
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
958958
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
@@ -982,8 +982,9 @@
982982
phys = <&combphy2 PHY_TYPE_PCIE>;
983983
phy-names = "pcie-phy";
984984
power-domains = <&power RK3568_PD_PIPE>;
985-
ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
986-
0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
985+
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
986+
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
987+
<0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
987988
resets = <&cru SRST_PCIE20_POWERUP>;
988989
reset-names = "pipe";
989990
#address-cells = <3>;

‎arch/arm64/boot/dts/rockchip/rk3588s.dtsi‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -229,6 +229,7 @@
229229
cache-line-size = <64>;
230230
cache-sets = <512>;
231231
cache-level = <2>;
232+
cache-unified;
232233
next-level-cache = <&l3_cache>;
233234
};
234235

@@ -238,6 +239,7 @@
238239
cache-line-size = <64>;
239240
cache-sets = <512>;
240241
cache-level = <2>;
242+
cache-unified;
241243
next-level-cache = <&l3_cache>;
242244
};
243245

@@ -247,6 +249,7 @@
247249
cache-line-size = <64>;
248250
cache-sets = <512>;
249251
cache-level = <2>;
252+
cache-unified;
250253
next-level-cache = <&l3_cache>;
251254
};
252255

@@ -256,6 +259,7 @@
256259
cache-line-size = <64>;
257260
cache-sets = <512>;
258261
cache-level = <2>;
262+
cache-unified;
259263
next-level-cache = <&l3_cache>;
260264
};
261265

@@ -265,6 +269,7 @@
265269
cache-line-size = <64>;
266270
cache-sets = <1024>;
267271
cache-level = <2>;
272+
cache-unified;
268273
next-level-cache = <&l3_cache>;
269274
};
270275

@@ -274,6 +279,7 @@
274279
cache-line-size = <64>;
275280
cache-sets = <1024>;
276281
cache-level = <2>;
282+
cache-unified;
277283
next-level-cache = <&l3_cache>;
278284
};
279285

@@ -283,6 +289,7 @@
283289
cache-line-size = <64>;
284290
cache-sets = <1024>;
285291
cache-level = <2>;
292+
cache-unified;
286293
next-level-cache = <&l3_cache>;
287294
};
288295

@@ -292,6 +299,7 @@
292299
cache-line-size = <64>;
293300
cache-sets = <1024>;
294301
cache-level = <2>;
302+
cache-unified;
295303
next-level-cache = <&l3_cache>;
296304
};
297305

@@ -301,6 +309,7 @@
301309
cache-line-size = <64>;
302310
cache-sets = <4096>;
303311
cache-level = <3>;
312+
cache-unified;
304313
};
305314
};
306315

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